System IC Design: Timing Issues and DFT. Hung-Chih Chiang

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1 System IC esign: Timing Issues and FT Hung-Chih Chiang

2 Outline SoC Timing Issues Timing terminologies Synchronous vs. asynchronous design Interfaces and timing closure Clocking issues Reset esign for Testability (FT) SoC Test Plan Scan, ATPG, memory BIST FT design rules 2

3 SoC Clock Issues ata Cache Instr. Cache Clock/OSC Microprocessor Memory High Speed I/O Ctrl High Speed Bus Memory Ctrl HS IP Bus Bridge Peripheral Bus Timer Intr Ctrl GPIO UART LS I/O Clock/OSC 3

4 SoC Clock omains CLK2 OSC Clock Generator CLK1 CLK3 CLK4 CLK6 CLK5 4

5 Timing Terminologies Setup time, hold time, release time, width, period and skew Cell delay and wire delay Best case, typical case, worst case and pseudo worst case Loading and driving capacity 5

6 Basic Cell Timings SN N RN Interconnection elay IA IB O Cell elay Cell elay Setup Hold Recovery Width Width Skew RN 1 Period 2 6

7 Best, Typical, Worst & Pseudo Worst Cases Best Case highest operation voltage, lowest temperature, fast process eg. 0 C, fast process Typical Case standard operation voltage, room temperature, typical process eg. 25 C, typical process Pseudo Worst Case lowest operation voltage, highest temperature, typical process eg. 125 C, typical process Worst Case lowest operation voltage, highest temperature, slow process eg. 125 C, slow process 7

8 Loading and Cell elay Linear elay Model t typical = t intrinsic + (K load * C load ) (atabook) Non-Linear elay Model (Table Lookup) t typical = F(t rf, C load ) (EA Timing Model) 8

9 Cell atasheet: NAN2 (1) 9

10 Cell atasheet: NAN2 (2) 10

11 Cell atasheet: FF (1) 11

12 Cell atasheet: FF (2) 12

13 Cell atasheet: FF (3) 13

14 Clock-Based Timing (single clock source) d 1 d 2 combination logic d 1 + d 2max < T t setup d 1 + d 2min > t hold 14

15 Outline SoC Timing Issues Timing terminologies Synchronous vs. asynchronous design Interfaces and timing closure Clocking issues Reset esign for Testability (FT) SoC Test Plan Scan, ATPG, memory BIST FT design rules 15

16 Synchronous vs. Asynchronous esign Synchronous esign Flip-flop based (clock based) Easy timing handling FT compliant Asynchronous Latch based Timing ambiguity cause problems Not FT compliant 16

17 Flip-Flop (Clock) Based esign combination logic Poor HL coding of combination logics can produce unintentional latches Avoid using flip-flops with enable input Use positive clock edge trigger for flip-flops for module RTL coding if flip-flops in cell library is triggered at positive clock edge 17

18 Flip-Flop Clock Edge If negative edge triggered flip-flops are required in a design while Cell Library contains positive edge triggered flip-flops, invert the clock phase first and then write RTL codes using positive edge triggered flip-flops to avoid inverters being inserted at clock inputs of each modules during logic synthesis. 18

19 Problem of Latch: timing ambiguity in E E output setup output setup 19

20 Problem of Latch: possible /E race E E E Need to ensure there is enough hold time for after the falling edge of E 20

21 Problem of Latch: FT scan_enable E scan path normal operation path is generally not controllable by due to E => A latch can not be part of a scan chain 21

22 Outline SoC Timing Issues Timing terminologies Synchronous vs. asynchronous design Interfaces and timing closure Clocking issues Reset esign for Testability (FT) SoC Test Plan Scan, ATPG, memory BIST FT design rules 22

23 Interfaces and Timing Closure A proper design of block interfaces makes timing closure a local problem. A major timing issue in deep submicron technology is the wire delay due to wire load capacitance and RC delay can be much larger than intrinsic cell delays. Timing driven APR helps deal with this problem by taking into account the wire load model. Physical synthesis takes a further stride in achieving timing closure by combining synthesis and timing driven placement. 23

24 Macro Interfaces Macro A Macro B Both inputs and outputs should be registered. This gives a full clock cycle to propagate the outputs of one macro to inputs of another. 24

25 Sub-block Interfaces Subblock Macro AA Subblock B Any block that is synthesized as a unit should have its own outputs registered. Any block that is floorplanned as a unit should have its own inputs and outputs registered. 25

26 Example: interface specification 3ns 3ns T on t care Valid on t care 26

27 Example: registered vs. unregistered inputs d 1 + t setup < 3ns? Combination d 2 + t setup < 3ns Combination 27

28 Outline SoC Timing Issues Timing terminologies Synchronous vs. asynchronous design Interfaces and timing closure Clocking issues Reset esign for Testability (FT) SoC Test Plan Scan, ATPG, memory BIST FT design rules 28

29 Clocking Issues Clock skew and clock tree ivided clocks Asynchronous clock interface Clock gating Synchronize Hard IP Other considerations 29

30 Clock Skew in Combination FF0/ FF1/ FF0/ Skew FF1/ 30

31 Clock Skew May Cause Errors in FF0/ FF1/ in in FF0/ FF0/ 0 0 FF1/ FF1/

32 Clock Tree Insert clock tree during APR Clock tree can significantly increase power consumption 32

33 Clock Tree Example Match + Skew 33

34 Clock Tree Example 34

35 ivided Clocks 1 (f/2 Hz) 1 +skew 1 Module A Clock Generator 0 (f Hz) 0 +skew 0 Module B t0 t1 t2 Ck2 (f/4 Hz) 2 +skew 2 Module C

36 An Alternative esign Approach for a ivided Clock omain +skew Module A En1 Clock Generator Ck Module B En2 Module C En1 En2 36

37 Asynchronous Clock Interface d b X Y a a 1a Ck2 Combination Z b b 1b d a Ck1 Block 1 angerous design!!! Random logic errors may occur due to the delay time difference between d a and d b. 37

38 Asynchronous Errors 2 X Y (a) Z (b) 1/CLK2 E.g. 01 X=0 X=1 X=0/1 01 X=1/

39 Clock Synchronization in Synchronization in Ck2 Ck1 Block A Not all asynchronous inputs need to be synchronized! A single flip-flop may not be good enough for clock synchronization. 39

40 ASIC Flip-Flop N N N N 40

41 Metastability 41

42 Standard Asynchronous Interface in Ck2 Ck1 Block A Two staged flip-flop to reduce the probability of metastability 42

43 ual Flip-Flop Synchronization 43

44 Peak Power Reduction A Sync. I/F Clock Generator Ck B Sync. I/F Sync. I/F C Cka A Clock Generator Ckb Ckc B C Async. I/F Async. I/F Async. I/F a b c 44

45 Clock Gating For Low Power esign Module A Clock Generator Module B Module C Clock Enable 45

46 Clock elays For Hard Blocks 1 +skew 1 Clock Generator 2 +skew 2 Take into account insertion delays of hard macros 46

47 Bypass PLL & Clock Gating For ebugging Clock PLL Test_en Clock Gate_en or Test_en 47

48 Clock Planning Guidelines The system clock generation and control logic should be separate from all function blocks of the system ocument clock domain information - frequencies, PLL - interface timing (input and output) - skew requirement among clocks Use the standard synchronization interface for asynchronous inputs Compensate insertion delays of hard macros Bypass clock gating and PLL in test mode 48

49 Outline SoC Timing Issues Timing terminologies Synchronous vs. asynchronous design Interfaces and timing closure Clocking issues Reset esign for Testability (FT) SoC Test Plan Scan, ATPG, memory BIST FT design rules 49

50 Chip Reset Issues Synchronous or Asynchronous? External or Internal Power On Reset? Voltage etector for Power own Reset? Hard Reset and Soft Reset? Each Module Individually Resettable for ebugging Purposes? 50

51 Synchronous Reset Reset N N N Easy to synthesize since reset is treated as a logic signal Reset slightly affect data timing Need at least one active clock edge for reset to take place. This could become a problem at power on 51

52 Asynchronous Reset N N N RN SN RN No clock required during reset period Reset does not affect data timing Like clock, a reset tree is usually required during APR 52

53 Avoid logical signal reset N N RN RN Avoid using a logic signal as a reset signal 53

54 Reset Guideline Asynchronous reset is preferred. Reset must be synchronously deasserted so that all state machine flipflops starts at the same active clock edge. All flip-flops/latches should be reset to a pre-defined state ( 0 or 1 ) to avoid ambiguity voltage output of sequential elements. 54

55 Outline SoC Timing Issues Timing terminologies Synchronous vs. asynchronous design Interfaces and timing closure Clocking issues Reset esign for Testability (FT) SoC Test Plan Scan, ATPG, memory BIST FT design rules 55

56 esign For Testability IC testing vs. verification - manufacturing defect vs. functional defect Importance of IC testing -cost of RMA Test phases: - wafer test (Chip Probing), - final test (packaged IC testing) Test principle: - different kinds of blocks require different test strategies - use a test controller at top level to sequence the test of different function blocks 56

57 An Example of SoC Test Plan T_ T_M S_I S_O Test Mode Register Test Circuits Test Mode: Processor Test RAM BIST ROM Check Sum SCAN/ATPG Functional Test Analog Macros... 57

58 SCAN Chain & ATPG Reset_n Scan_en RN N N SN combination logic 58

59 Memory BIST Software Memory BIST Hardware Memory BIST A/i/En clock test_crtl Pattern Generator A//En Memory Module Compressor o q So 59

60 FT Guidelines - 1 Avoid internally gated clocks or derived clocks Clock Gated clock erived clock 60

61 FT Guidelines - 2 Avoid using latches Controllable E Uncontrollable A latch can not be inserted into a scan chain due to the uncontrollable enable input 61

62 FT Guidelines - 3 Avoid using flip-flops with an enable input (synthesis) E Enable is not controllable 62

63 FT Guidelines - 4 Avoid combinational feedback Race/unstable ATPG is not applicable 63

64 FT Guidelines - 5 Avoid uncontrollable asynchronous signals N RN Uncontrollable 64

65 FT Guidelines - 6 Avoid feeding data path with clocks N RN 65

66 FT Guidelines - 7 Provide test control for uncontrollable signals Clock PLL Clock Test_en Gate_en or Test_en 66

67 Summaries Recommend flip-flop based design. Use Latches only when you know what you are doing. A proper design of block interfaces makes timing closure a local problem. Clock domains require special cares. A global reset signal is recommended. A proper SoC test plan is important to reduce RMA costs. FT rules must be followed to ensure the testability of designs. 67

System IC Design: Timing Issues and DFT. Hung-Chih Chiang

System IC Design: Timing Issues and DFT. Hung-Chih Chiang Wireless Information Transmission System Lab. System IC esign: Timing Issues and FT Hung-Chih Chiang Institute of Communications Engineering National Sun Yat-sen University SoC Timing Issues Outline Timing