Sequential Circuit W CLK. CMSC 2833 Lecture 42. Steps:
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1 . ynchronous equential Circuit Design CMC 8 Lecture ynchronous equential Circuit Design teps:. Read the problem specification and reduce to a block diagram.. Find the block that is a sequential circuit and draw a symbolic state diagram.. Develop a symbolic PREENT NET TATE table.. Determine the number of flip-flops, assign states, and revise the PREENT NET TATE table.. Develop a NET TATE DECODER for several kinds of flip-flops.. Plot the NET TATE DECODERs and determine which kind of flip-flop minimizes the logic for the NET TATE DECODER.. Plot the output decoder logic. 8. Draw the logic diagram. Example: Problem pecification: Design a circuit having a single binary input (witch) and two binary outputs ZZ and WW. When the switch is in the up-position the outputs ZZZZ =. When the circuit senses that the switch has been moved to the down-position, the output is to sequence, on the rising edge of successive clock pulses, from ZZZZ = to ZZZZ = to ZZZZ = to ZZZZ = and then stop and hold until the switch is moved back to the up-position again, at which time the ZZZZ code reverts to ZZZZ =.. Read the problem specification and reduce to a block diagram. CLK equential Circuit Z W Block Diagram
2 . ynchronous equential Circuit Design CMC 8 Lecture. Find the block that is a sequential circuit and draw a symbolic state diagram. a / / b / c / / d / ymbolic tate Diagram. Develop a symbolic PREENT NET TATE table. PREENT TATE INPUT NET TATE OUTPUT ZZ WW a b a b c c c d d d d a
3 . ynchronous equential Circuit Design CMC 8 Lecture. Determine the number of flip-flops, assign states, and revise the PREENT NET TATE table. a / / b c d / / / tate Diagram / Present tate Input Next tate Output Name # AA BB Name AA BB ZZ WW a b a b c c d d a c d d
4 . ynchronous equential Circuit Design CMC 8 Lecture. Plot the NET TATE DECODERs and determine which kind of flip-flop minimizes the logic for the NET TATE DECODER. Present tate Input Next tate Next tate Decoder AA BB AA BB DD AA DD BB JJ AA KK AA JJ BB KK BB (tt) (tt + ) JJ KK JK Flip-Flop Excitation Table. Develop a NET TATE DECODER for several kinds of flip-flops. D A D B DD AA = BB + AA DD BB = AA + AB Z W ZZ = AA WW = BB
5 . ynchronous equential Circuit Design CMC 8 Lecture J A K A JJ AA = BB KK AA = BB J B K B JJ BB = AA KK BB = AA. Plot the output decoder logic. Present tate Input Next tate Output Name # AA BB Name AA BB ZZ WW a b a b c c d d a c d d Z W ZZ = AA WW = BB
6 . ynchronous equential Circuit Design CMC 8 Lecture 8. Draw the logic diagram. A A B B J K CK B W J K CK A Z CLK Logic Diagram
7 . ynchronous equential Circuit Design CMC 8 Lecture Problem pecification: Design a counter that when switch is off (), counts,,,,, and when the switch is on (), counts,,,,. When the counter is in state and the switch is on (), the counter switches to an odd state. When the counter is in state and the switch is off (), counter switches to an even state. Define two outputs and YY such that they display the values of the counter in binary. For example, when the counter is in state, =, that is, = and YY =.. Read the problem specification and reduce to a block diagram. CLK Counter Circuit Y.. Analyze the problem Block Diagram # AA BB # AA BB Present tate Input Next tate # AA BB # AA BB =, =, oooooo =, eeeeeeee =, =, =,
8 . ynchronous equential Circuit Design CMC 8 Lecture D A D B DD AA = AA DD BB = Present tate Input Next tate Output # AA BB # AA BB YY 8
9 . ynchronous equential Circuit Design CMC 8 Lecture. Find the block that is a sequential circuit and draw a symbolic state diagram. / / / / / / / / ymbolic tate Diagram Well, it is not too symbolic. Develop a symbolic PREENT NET TATE table. Present tate Input Next tate Output # AA BB # AA BB YY. Determine the number of flip-flops, assign states, and revise the PREENT NET TATE table. Yes, we already did that task. 9
10 . ynchronous equential Circuit Design CMC 8 Lecture. Plot the NET TATE DECODERs and determine which kind of flip-flop minimizes the logic for the NET TATE DECODER. Present tate Input Next tate Next tate Decoder AA BB AA BB DD AA DD BB JJ AA KK AA JJ BB KK BB (tt) (tt + ) JJ KK JK Flip-Flop Excitation Table. Develop a NET TATE DECODER for several kinds of flip-flops... D Flip-Flops D A D B DD AA = AA DD BB =
11 . ynchronous equential Circuit Design CMC 8 Lecture.. JK Flip-Flops Present tate Input Next tate Next tate Decoder AA BB AA BB DD AA DD BB JJ AA KK AA JJ BB KK BB J A K A JJ AA = KK AA = J B K B JJ BB = KK BB =
12 . ynchronous equential Circuit Design CMC 8 Lecture. Plot the output decoder logic. Present tate Input Next tate Output # AA BB AA BB # YY Y = AA YY =
13 . ynchronous equential Circuit Design CMC 8 Lecture 8. Draw the logic diagram. A A B B D CK B D CK A CLK Y Logic Diagram
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