A 90 Gb/s 2:1 Multiplexer with 1 Tap FFE in SiGe Technology

Transcription

1 A 90 Gb/s 2:1 Multiplexer with 1 Tap FFE in SiGe Technology Ekaterina Laskin, University of Toronto Alexander Rylyakov, IBM T.J. Watson Research Center October 14 th, 2008 Paper H4

2 Outline Motivation System operation and block diagram Transistor level schematics Test setup Measurement results Summary October 14th, 2008 Paper H4 2 of 27

3 Motivation Demonstrate SiGe technology capabilities Wireline link at > 80 Gb/s with only 1 channel TX that equalizes pre cursor ISI and its own loss Impulse Response of Measured Coax. Cable at 90Gb/s 1 Amplitude (A. U.) pre cursor (TX) post cursor (RX) Time (UI), 1 UI = 11.1ps October 14th, 2008 Paper H4 3 of 27

4 System 110 Gb/s attenuation = 55GHz 300mV 100mV data 2:1 MUX channel 1:2 DeMUX 100mV 300mV 0 20ps 40ps 300mV 100mV 100mV 300mV 0 10ps 20ps 200mV 100mV 0mV 100mV 200mV 0 10ps 20ps October 14th, 2008 Paper H4 4 of 27

5 System 110 Gb/s attenuation = 55GHz 300mV data 2:1 MUX + FFE channel 1:2 DeMUX 100mV 100mV 300mV 100mV 100mV 300mV 0 10ps 20ps 300mV 0 20ps 40ps 80mV 40mV 0mV 40mV 80mV 0 10ps 20ps October 14th, 2008 Paper H4 5 of 27

6 Top Level Schematics IN1 IN0 clock tree EF EF 2:1 MUX INV D Q D Q D Q INV D Q D Q SEL OUT IN1 IN0 EF EF secondary path (weaker) primary path INV INV D Q D Q D Q D Q BUF BUF D Q D Q D Q SEL tap SEL OUT CLOCK EF clock tree CLOCK EF 2:1 MUX 2:1 MUX with FFE October 14th, 2008 Paper H4 6 of 27

7 ECL Latch Schematic CLK Vbias IN OUT 3.3V October 14th, 2008 Paper H4 7 of 27

8 Final Latch Schematic CLK OUT Vbias IN 3.3V 2 versions: 23mA & 29mA Cherry Hooper amplifier in the latch core for peaking Separate EFs for feedback and output October 14th, 2008 Paper H4 8 of 27

9 Clock/Data Buffer Schematics IN Vbias OUT Vbias OUT IN Clock Buffer 3.3V 3.3V Data Buffer Clock buffers: CH amplifiers with EF for level shifting Data buffers: CH amplifiers with inductive peaking October 14th, 2008 Paper H4 9 of 27

10 Selector Schematic MUX CLK OUT Vb IN1 IN0 Vb 3.3V ECL selector with I TAIL = 8mA Cascode 50Ω output buffer October 14th, 2008 Paper H4 10 of 27

11 Selector Schematic MUX+FFE OUT primary selector 50Ω secondary selector CLK CLK Vb IN1 IN0 IN0 IN1 Vb 8mA tap weight 4mA 3.3V 2 selectors driving the same load, current control Output buffer omitted because it limits the BW October 14th, 2008 Paper H4 11 of 27

12 Die Photos IBM s SiGe8HP: f T =210GHz, f MAX =260GHz, 5 metals 1.66mm 1.66mm 1.66mm 1.66mm 2:1 MUX 2:1 MUX with FFE October 14th, 2008 Paper H4 12 of 27

13 Die Photos 2:1 MUX Clock tree Input buffers Latches Selector Output buffer 2:1 MUX Clock tree Data buffers Input buffers Selectors Latches 2:1 MUX with FFE October 14th, 2008 Paper H4 13 of 27

14 Test Setup bit pattern generator oscilloscope BER analyzer divider cable to equalize clock source October 14th, 2008 Paper H4 14 of 27

15 Test Setup divider CW signal source scope pattern generator error detector long cable October 14th, 2008 Paper H4 15 of 27

16 35.5mV 2:1 MUX Operation 3.5ps 2.0ps 30.4mV 90 Gb/s PRBS pattern Precision timebase trigger With 70 GHz remote head 92 Gb/s PRBS pattern Precision timebase Without remote head October 14th, 2008 Paper H4 16 of 27

17 2:1 MUX with FFE No Cable 35.5mV 3.5ps 35.5mV 3.5ps 90 Gb/s, PRBS Equalization fully OFF 90 Gb/s, PRBS Equalization fully ON Equalizer tap operation without long cable at output October 14th, 2008 Paper H4 17 of 27

18 Cable Characteristics 0 5 Cable 1 (108 inch = 2.74m) Cable 2 (156 inch = 3.96m) S 21 (db) Frequency (GHz) Ripples due to multiple connectors October 14th, 2008 Paper H4 18 of 27

19 2:1 MUX with FFE 108 Cable 20mV 4.5ps 20mV 4.5ps 80 Gb/s, PRBS Equalization fully OFF 80 Gb/s, PRBS Equalization fully ON October 14th, 2008 Paper H4 19 of 27

20 2:1 MUX with FFE 108 Cable 20mV 4.0ps 20mV 4.0ps 90 Gb/s, PRBS Equalization fully OFF 90 Gb/s, PRBS Equalization fully ON October 14th, 2008 Paper H4 20 of 27

21 2:1 MUX with FFE 108 Cable 50mV RX eye 4.0ps 50mV RX eye 4.0ps TX eye TX eye 90 Gb/s, PRBS Equalization fully OFF 90 Gb/s, PRBS Equalization fully ON October 14th, 2008 Paper H4 21 of 27

22 2:1 MUX with FFE 108 Cable BER measurements are limited by available BERT Input PRBS Data Rate 10 Gb/s Measured BER < Gb/s < Gb/s < Gb/s < October 14th, 2008 Paper H4 22 of 27

23 2:1 MUX with FFE 156 Cable 20mV 5.0ps 20mV 5.0ps 80 Gb/s, PRBS Equalization fully OFF 80 Gb/s, PRBS Equalization fully ON October 14th, 2008 Paper H4 23 of 27

24 2:1 MUX with FFE 156 Cable 50mV RX eye 5.0ps 50mV RX eye 5.0ps TX eye TX eye 80 Gb/s, PRBS Equalization fully OFF 80 Gb/s, PRBS Equalization fully ON October 14th, 2008 Paper H4 24 of 27

25 Performance Summary Bitrate Bit Error Rate RMS Jitter P P Jitter Eye Amplitude Rise Time Fall Time Supply Power Consumption 2:1 MUX 0 92 Gb/s Not measured 769 fs 4.1 fs 146 mv 8.8 ps 6.9 ps 3.3 V 1.25 W 2:1 MUX with FFE 0 90Gb/s < at 40 Gb/s 643 fs 3.6 ps mv 3.1 ps 3.8 ps 3.3 V 1.94 W October 14th, 2008 Paper H4 25 of 27

26 Conclusion Cherry Hooper amplifiers for BW extension 2:1 multiplexer up to 92 Gb/s (limited by source) 2:1 multiplexer with 1 tap FFE Equalizes 12 db (108 inch cable) at 90 Gb/s Equalizes 14 db (156 inch cable) at 80 Gb/s BER < at 40 Gb/s through 108 inch cable World's fastest TX with a 1 tap digital equalizer Can be used in a >80 Gb/s serial wireline link October 14th, 2008 Paper H4 26 of 27

27 Acknowledgements IBM T.J. Watson Research Center Brian Floyd Daniel Friedman Brian Gaucher Sudhir Gowda Dong Kam Scott Reynolds MehmetSoyuer Sorin Voinigescu Project supported by DARPA (contracts N C 8014 and N C 8013) October 14th, 2008 Paper H4 27 of 27

28 Extra Slides October 14th, 2008 Paper H4 28 of 27

29 2:1 MUX Operation 80 Gb/s PRBS pattern Left Module trigger 80 Gb/s PRBS pattern Precision timebase October 14th, 2008 Paper H4 29 of 27