ENG2410 Digital Design Registers & Counters

Transcription

1 ENG2410 Digital Design Registers & Cunters Registers: Definitin Register a set f flip-flps May include extensive lgic t cntrl state transitin Registers als refer t fast memry fr string data in a cmputer Fall 2017 S. Areibi Schl f Engineering University f Guelph 4 Week #8 Tpics Definitin f Register and Cunter Registers, Shift Registers Ripple Cunters Synchrnus Binary Cunters BCD Cunters Cunters: Definitin Cunter Register that ges thrugh sequence f states as it is clcked We designed a simple cunter in the previus Lecture using T Flip Flps! Resurces Simple Register (N External Gates) Chapter #7, Man Sectins 7.1 Registers and Lad Enable 7.6 Shift Registers 7.6 Ripple Cunters 7.6 Synchrnus Binary Cunters Inputs Outputs Functinality Stre D (D 0,D 1,D 2,D 3 ) On ps-edge f Clck Clear signal nrmally high Pwer-up reset 3 6 Schl f Engineering 1

2 Disabling the Clcking Shift Registers 7 10 Clcking Shift Registers The transfer f new inf int a register is referred t as lading the register. Typically we dn t want t lad every clck We gate the clck!! (Disable the clck)!! We try t avid gating!! (Timing issues) A shift register is a chain f flip-flps in cascade, with the utput f ne flip-flp cnnected t the input f the next flip-flp. It is a register capable f shifting its stred bits laterally in ne r bth directins. All flip-flps receive a cmmn clck pulse, which activates the shift frm each stage t the next. Disable the Clck 8 11 Alternative Simple 4-bit Shift Register If lad H, then D ges thrugh Otherwise, Q is fed back Keep same value N clck gating Every bit shifts t the right at every clck edge. Why add all this lgic? Because D FF desn t have n change behavir New infrmatin will enter via S i and leave frm S 9 12 Schl f Engineering 2

3 Simple 4-Bit Shift Register: Diagram Schematic Clcked in cmmn Just serial in and serial ut Q 0 Q 1 Q 2 Q 3 SO One stage f a bidirectinal shift register with parallel lad VHDL fr Shift Registers Shift Register with Parallel Lad -- 4 bit Shift Register with Reset library ieee; use ieee.std_lgic_1164.all; entity srg_4_r is prt (CLK, RESET, SI : in std_lgic; Q : ut std_lgic_vectr(3 dwnt 0); SO : ut std_lgic); end srg_4_r; architecture behaviral f srg_4_r is Signal shift : std_lgic_vectr(3 dwnt 0); begin prcess (CLK, RESET) begin if (RESET = `1 ) then shift <= `0000 ; elsif (CLK event and CLK = `1 )) then shift<= shift(2 dwnt 0) & SI; end if; end prcess; Q <= shift; S0 <= shift(3); end behaviral; Reset Lad any value t the shift register The shift register can then shift infrmatin ne bit at a time Bidirectinal Shift Register Shift Register with Parallel Lad Shift either way Nw we have fllwing pssible inputs Parallel lad Shift frm left Shift frm right Als n change Schematic Schl f Engineering 3

4 Shift Registers (Summary) Hardware Cmparisn Capability t shift bits In ne r bth directins Usage? Part f standard CPU instructin set Cheap Multiplicatin/Divisin Serial cmmunicatins Serial vs. parallel adder One full adder vs. n adders Serial takes n clck cycles, parallel nly ne clck cycle Serial Additin Synchrnus Cunters Initially reset all registers Register A accumulates At same time, new value ging int B Serial Additin Adds ne bit at a time Then shift thrugh adder int A. Added t 0 if A is empty. Cunters Cunter is a register but has states Als ges thrugh sequence f states cunts n clck r ther pulses Examples: Binary Cunter Cunts thrugh binary sequence n bit cunter cunts frm 0 t 2 n 1 BCD Cunter Any Sequence Cunter Shift value in serially Stres carry ne clck Schl f Engineering 4

5 Synthesis Using T Flip Flps T Flip Flps Synchrnus Design a cunter that cunts frm 000 t 111 and then back t 000 again. Use T Flip-Flps By using K-maps we can minimize the flip flp input equatins. T A 2 T A 1 1 T A A Cunter using T Flip Flps Synchrnus Cunters Asynchrnus Cunters Example: T Flip Flp Synthesis Asynchrnus Cunters 0 Asynchrnus cunters are yet anther type f cunters where nt all flip flps are driven by the glbal clck. Ripple cunters are asynchrnus cunters that are easy t design Schl f Engineering 5

6 Ripple Cunter Simple (Asynch) Tggle Cunters with Parallel Lad BCD Cunters Binary Cunter with Parallel Lad BCD Cunters Cunters emplyed in digital systems quite ften require a parallel-lad capability fr transferring an initial binary number int the cunter prir t the cunter peratin. When lad is equal t 1, the input lad cntrl disables the cunt peratin and causes a transfer f data frm the fur parallel inputs t the fur utputs. The carry utput C0 becmes a 1 if all flip-flps are equal t 1 while the cunt input is enabled. This feature is useful fr expanding the cunter t mre stages BCD Cunters can als be designed using individual flip-flps and gates Schl f Engineering 6

7 BCD Cunter using Binary Cunters Circuit and State Diagram The Binary Cunter with parallel lad can be cnverted int a synchrnus BCD cunter (Hw?) By cnnecting an external AND gate t the lad cntrl (as shwn in the Figure) Arbitrary Cunters VHDL fr Cunters Arbitrary Cunt Sequence VHDL fr Cunters One mre type f cunter is useful Cunt an arbitrary sequence Maybe yu need a sequence f states -- 4 bit Binary Cunter with Reset library ieee; use ieee.std_lgic_1164.all; entity cunt_4_r is prt (CLK, RESET, EN : in std_lgic; Q : ut std_lgic_vectr(3 dwnt 0); CO : ut std_lgic); CLK RESET Q 3 Q 2 Q 1 Q 0 end cunt_4_r; EN CO architecture behaviral f cunt_4_r is Signal cunt : std_lgic_vectr(3 dwnt 0); begin prcess (CLK, RESET) begin if (RESET = `1 ) then cunt <= `0000 ; elsif (CLK event and CLK = `1 ) and (EN = `1 )) then cunt <= cunt ; end if; end prcess; q <= cunt; C0 <= `1 when cunt = 1111 and EN = `1 else 0 ; end behaviral; Schl f Engineering 7

8 Example II 46 Serial Transfer (8-bit Shift Register) Example II.. Cntinue Culd shift data in What s n wire at each clck? Clcked 4 times Table Shwing Shift 45 Schl f Engineering 8