Fundamentals of Computer Systems
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1 Fundamentals of Computer Systems Sequential Logic Stephen A. Edwards Columbia University Fall 2012
2 State-Holding Elements
3 Bistable Elements Equivalent circuits; right is more traditional. Two stable states:
4 A Bistable in the Wild This debounces the coin switch. Breakout, Atari 1976.
5 S Latch S S
6 S Latch 0 1 S 1 0 S S Set
7 S Latch 0 1 S 0 0 S S Hold, State 1
8 S Latch 1 0 S 0 1 S S eset
9 S Latch 0 0 S 0 1 S S Hold, State 0
10 S Latch 1 0 S 1 0 S S Huh?
11 S Latch 0 1 S 1 0 S S Set
12 S Latch 0 1 S 0 0 S S Hold, State 1
13 S Latch 1 0 S 1 0 S S Huh?
14 S Latch 0 X S 0 X S S Undefined
15 S Latches in the Wild Generates horizontal and vertical synchronization waveforms from counter bits. Stunt Cycle, Atari 1976.
16 Latch C C inputs outputs C 0 X
17 A Challenge A simple traffic light controller. Want the lights to cycle green-yellow-red. C C Y C G oes this work?
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30 Positive-Edge-Triggered Flip-Flop C M Master C Slave C S C C C C M transparent C S opaque
31 Positive-Edge-Triggered Flip-Flop C M Master C Slave C S C C C C M transparent C S opaque
32 Positive-Edge-Triggered Flip-Flop C M Master C Slave C S C C C C M C S transparent opaque opaque transparent
33 Positive-Edge-Triggered Flip-Flop C M Master C Slave C S C C C C M C S transparent opaque opaque transparent
34 Positive-Edge-Triggered Flip-Flop C M Master C Slave C S C C C C M transparent opaque transparent C S opaque transparent opaque
35 Positive-Edge-Triggered Flip-Flop C M Master C Slave C S C C C C M transparent opaque transparent opaque C S opaque transparent opaque transparent
36 The Traffic Light Controller: A second try Let s try this again with flip-flops. Y G Y G
37 The Traffic Light Controller: A second try Let s try this again with flip-flops. Y G Y G
38 The Traffic Light Controller: A second try Let s try this again with flip-flops. Y G Y G
39 The Traffic Light Controller: A second try Let s try this again with flip-flops. Y G Y G
40 The Traffic Light Controller: A second try Let s try this again with flip-flops. Y G Y G
41 The Traffic Light Controller with eset ESET Y G ESET Y G
42 The Traffic Light Controller with eset ESET Y G ESET Y G
43 The Traffic Light Controller with eset ESET Y G ESET Y G
44 The Traffic Light Controller with eset ESET Y G ESET Y G
45 The Traffic Light Controller with eset ESET Y G ESET Y G
46 The Traffic Light Controller with eset ESET Y G ESET Y G
47 Flip-Flop with Enable 0 1 E C C E 0 X X X 1 X X E C What s wrong with this solution?
48 Asynchronous Preset/Clear PE CL PE CL
49 The Traffic Light Controller w/ Async. eset ESET PE CL PE CL Y PE CL G
50 The Synchronous igital Logic Paradigm Gates and flip-flops only INPUTS OUTPUTS Each flip-flop driven by the same clock STATE C L Every cyclic path contains at least one flip-flop CLOCK NEXT STATE
51 Cool Sequential Circuits: Shift egisters A A X X X X 1 0 X X X X X X
52 Universal Shift egister L S 1 S0 S 1 S L S 1 S 0 Operation 0 0 Shift right 0 1 Load 1 0 Hold 1 1 Shift left
53 Cool Sequential Circuits: Counters Cycle through sequences of numbers, e.g.,
54 The 74LS163 Synchronous Binary Counter
55 Timing in Synchronous Circuits C L t c t c : Clock period. E.g., 10 ns for a 100 MHz clock
56 Timing in Synchronous Circuits C L Sufficient Hold Time? t p(min,ff) t p(min,cl) Hold time constraint: how soon after the clock edge can start changing? Min. FF delay + min. logic delay
57 Timing in Synchronous Circuits C L t p(max,ff) Sufficient Setup Time? t p(max,cl) Setup time constraint: when before the clock edge is guaranteed stable? Max. FF delay + max. logic delay
58 Clock Skew: What eally Happens C L 1 2 Sufficient Hold Time? 1 2 t skew t p(min,ff) t p(min,cl) 2 arrives late: clock skew reduces hold time
59 Clock Skew: What eally Happens C L 1 2 Sufficient Setup Time? 1 2 t skew t p(max,ff) t p(max,cl) 1 arrives early: clock skew reduces setup time
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Computer Science 324 Computer Architecture Mount Holyoke College Fall 2009 opic Notes: Sequential Circuits Let s think about how life can be bad for a circuit. Edge Detection Consider this one: What is
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Lecture 11: Sequential Circuit esign Outline q Sequencing q Sequencing Element esign q Max and Min-elay q Clock Skew q Time Borrowing q Two-Phase Clocking 2 Sequencing q Combinational logic output depends
Figure 1 shows a simple implementation of a clock switch, using an AND-OR type multiplexer logic.
1. CLOCK MUXING: With more and more multi-frequency clocks being used in today's chips, especially in the communications field, it is often necessary to switch the source of a clock line while the chip