Chapter. Sequential Circuits

Size: px

Start display at page:

Download "Chapter. Sequential Circuits"

Bridget Peters
6 years ago
Views:

1 Chapter Sequential Circuits

2 Circuits Combinational circuit The output depends only on the input Sequential circuit Has a state The output depends not only on the input but also on the state the circuit is in

3 Sequential circuit Constructed from standard gates, but with one or more feedback connections An unstable state is one that will change a few gate delays later because of the feedback connection A stable state is one that will persist indefinitely until the input changes

4 Figure. a b c d ( a) An unstable circuit. a b c ( b) A stable circuit.

5 SR Latch The SR latch has two stable states When SR =, output can be or depending on the state of the latch S = sets ouput to R = resets output to

6 Figure.2 R S

7 Figure.3 Time S R Stability Initial T g 2T g Stable Unstable Unstable Stable

8 Figure.4 Time S R Stability Initial Stable Stable

9 Figure.5 S R a b c d e

10 System clock Controls the state transitions of all the sequential circuits to happen at the same time Sequence of regularly spaced pulses with period T

11 Figure.6 T Ck

12 Clocked SR flip-flop Two AND gates that act as an enable Only when Ck is high can the S and R inputs affect the state of the flip-flop The effect is to digitize the time axis

13 Figure.7 R S Ck S R Ck ( a ) Block diagram. ( b) Implementation.

14 Figure.8 S R Ck a b c d e

15 The feedback problem Flip-flops are often used in circuits with feedback connections (in addition to the internal feetback in the latch) Therefore, unstable states are possible There are two design solutions to the feedback problem Edge-triggered flip-flops Master-slave flip-flops

16 Figure.9 Input Combinational circuit S Ck R Output

17 Master-slave SR flip-flop Solves the instability problem caused by possible external feedback Input goes to the master latch first, and then from the master to the slave, in four steps The threshold of a gate is the value of the input signal that causes the output to change Engineers can make gates with thresholds a little above or a little below the average value between and

18 S Ck R Figure. (a) Block diagram. Master Slave S Threshold V2 2 R2 R Threshold V2 2 S2 Ck Threshold V (b) Implementation.

19 Timing detail of a single Ck pulse t : Isolate slave from master t 2: Connect master to input t 3: Isolate master from input t 4: Connect slave to master

20 Figure. Clock signal V2 V t t 2 t 3 t 4 Time

21 Effect on timing The output changes on the falling edge of the Ck pulse and depends on the external SR input at that time

22 Figure.2 S R Ck

23 Characteristic table A truth table is not adequate to describe a flip-flop, because its output depends on more than its input Given the inputs at time t and the state at time t, the characteristic table shows the state at time t +, that is, after one clock pulse

24 Figure.3 S(t) R(t) (t) ( t + ) Condition No change Reset Set Not defined

25 Figure.4

26 Four common flip-flops SR JK D T Set/reset Set/reset/toggle Data or delay Toggle

27 Excitation table The excitation table is a design tool for constructing circuits from a given type of flip-flop Given the desired transition from (t) to (t +), what inputs are necessary to make the transition happen?

28 Figure.5 (t) (t + ) S(t) R(t)

29 JK flip-flop Resolves the undefined transition in the SR flip-flop When JK =, output can be or depending on the state of the latch J = sets ouput to (like S) K = resets output to (like R) JK = toggles from one state to the other

30 Figure.6 J(t) K(t) (t) (t + ) Condition No change J Ck Reset K Set Toggle (a) Block diagram. (b) Characteristic table.

31 JK flip-flop design Must design a three-input two-output combinational circuit Inputs J(t), K(t), (t) Outputs S(t), R(t)

32 Figure.9 Input Combinational circuit S Ck R Output

33 Design table Step : Given (t), J(t), and K(t), list the desired state after the transition (t + ) Step 2: Given (t) and (t + ), use the excitation table to list the required input for S(t) and R(t) Step 3: Use Karnaugh maps to design minimized two-level combinational circuits for S(t) and R(t)

34 S(t) R(t) (t + ) J(t) K(t) (t) Figure.7

35 Figure.8 JK JK (a) Karnaugh map for S. (b) Karnaugh map for R.

36 Figure.9 J K S Ck R Ck

37 D flip-flop The delay or data flip-flop Only one input, D Regardless of the current state (t), the state after the clock pulse (t + ) will be the same as D(t)

38 Figure.2 D(t) (t) (t + ) Condition D Delay Ck Delay (a) Block diagram. (b) Characteristic table. D Ck (c) A timing diagram.

39 Figure.2 (t) D(t) (t + ) S(t) R(t) (a) Design table. D D (b) Karnaugh map for S. (c) Karnaugh map for R.

40 Figure.22 D S Ck R Ck

41 T flip-flop The toggle flip-flop Only one input, T If T =, the state remains unchanged If T =, the state toggles from to or from to

42 Figure.23 T Ck (a) Block diagram. T(t) (t) (t + ) Condition No change Toggle (b) Characteristic table.

43 Flip-flop design Any given flip-flop can be constructed from any other flip-flop with the right combinational circuit Use the excitation table for the flip-flop from which you are constructing the given flip-flop

44 Figure.24 (t) (t + ) J(t) K(t) (t) (t + ) D(t) (a) The JK flip-flop. (b) The D flip-flop. (t) (t + ) T(t) (c) The T flip-flop.

45 General sequential circuits A general sequential circuit is an interconnection of gates and flip-flops The flip-flops are called state registers The current state and current input determine the current output The current state and current input determine the next state, that is, the state after one Ck clock pulse

46 Figure.25 Input Combinational circuit State registers Output Feedback

47 Figure.26 Input Sequential circuit? ( a) Analysis The input and sequential circuit are given. The output is to be determined. Input? Output ( b) Design The input and desired output are given. The sequential circuit is to be determined.

48 Sequential analysis Step : List all possible combinations of current state and current input in an analysis table Step 2: For each combination, compute the output and the current inputs to the state registers Step 3: From the characteristic table, determine the next state and construct the state transition table and diagram

49 Figure.27 X TA T FFA A Ck X2 TB T FFB B Ck B Y Ck

50 TA(t) TB(t) Y(t) A(t + ) B(t + ) X(t) X2(t) A(t) B(t) Figure.28

51 Figure.29 A(t) B(t) X(t) X2(t),,,,,,,,,,,,,,,, A(t + ) B(t + ), Y(t)

52 Figure.3 / / / / / / / / / / / / /, /, /, /

53 Asynchronous inputs An asynchronous input changes the state of a flip-flop immediately without regard to Ck Preset sets to Clear clears to Used to initialize the state of a machine

54 Figure.3 Preset S Ck R Clear

55 Sequential design Given the state transition diagram, the output, and the type of flip-flop to be used, design the combinational circuit Any unused input combinations or unused states are don t care conditions 2n states are possible with n flip-flops

56 Design steps Step : In a design table, list the initial state, input, and output, and from the transition diagram list the next state Step 2: Use the excitation table for the given type of flip-flop to determine the input required for the state registers Step 3: Use Karnaugh maps to design a minimized two-level circuit for each flip-flop input

57 Figure.32 / / / / / / / / / / / /

58 FFA Flip-flop input conditions FFB RB(t) SB(t) RA(t) SA(t) Next state Initial output Y(t) B(t + ) Initial Initial state input A(t) B(t) X2(t) X(t) A(t + ) Figure.33

59 Figure.34 X X2 X AB A B (a) SA = A X X2 (b) RA = A B X2 + A B X X2 X X X A B A B A B X2 X2 X2 (c) SB = B X (d) RB = B X + A X2 (e) Y = A X2 + A X X2

60 Figure.35 A B X2 A B X X2 B X A A X B X SA RA SB RB FFA S Ck R FFB S Ck R A A B B A X2 A X X2 Y X2 Ck

61 Register An example is the 6-bit accumulator in the Pep/8 CPU Constructed as an array of D flip-flops with a Load line that connects to each Ck input Data is clocked into the register in parallel

62 Figure.36 DataIn Load ( a) DataOut Block diagram. DataIn D D D D Ck Ck Ck Ck Load ( b) DataOut Implementation with D flip-flops.

63 Bus A bus is a group of wires connecting two subsystems With a unidirectional bus, data can flow in only one direction With a bidirectional bus, data can flow in both directions

64 Bidirectional bus Requires only half the number of wires between subsystems Problem: You can connect the inputs of two gates, but you cannot connect the outputs of two gates Solution: The tri-state buffer

65 Figure.37 Subsystem A Subsystem B Bus

66 Figure.38 E a x Disconnected Disconnected

67 Figure.39 Subsystem A Subsystem B E E Bus

68 Memory subsystems CS: Chip select, to enable or select the memory chip WE: Write enable, to write or store a memory word to the chip OE: Output enable, to enable the output buffer to read a word from the chip

69 Figure.4 A A A2 A3 A4 A5 D D D2 D3 D4 D5 D6 D7 A A A2 A3 A4 A5 A6 A7 A8 D CS WE OE CS WE OE (a) 64 8 bit memory chip. (a) 52 bit memory chip.

70 Memory access To store a word (memory write) Select chip by setting CS to Put data and address on the bus and set WE to To retrieve a word (memory read) Select chip by setting CS to Put address on the bus, set OE to, and read the data on the bus

71 D Ck D Ck Figure.4 Word D D Ck Ck A Word 2 4 decoder D D Ck Ck A Word 2 D D Ck Ck Word 3 WE MMV CS OE Read enable D Read enable D

72 Figure.4 (Expanded) D D Ck Ck Word 3 WE MMV CS OE Read enable D Read enable D

73 Figure.42 DW DR CS OE D

74 Figure.43 CS OE Operation Disconnected Disconnected Connect DR to D

75 Figure.44 Input Output Delay One shot

76 Memory types SRAM: Static random access memory DRAM: Dynamic RAM ROM: Read-only memory PROM: Programmable ROM EPROM: Erasable PROM EEPROM: Electrically erasable PROM Flash memory: A type of EEPROM

77 Constructing memory subsystems Two design problems How to combine several n m chips to make an n k module where k is greater than m How to combine several n m chips to make an l m module where l is greater than n the address decoding problem

78 Figure.45(a) A A D D D2 D3 D4 D5 D6 D7 CS WE OE (a) Block diagram.

79 Figure.45(b) A A A D A D A D A D A D A D A D A D CS WE OE D7 D6 D5 D4 D3 D2 D D (b) Implementation.

80 Address decoding An example with 8 address lines and four chips in an address space of 256 bytes 64-byte RAM at address 32-byte RAM at address 64 8-port I/O chip at address byte ROM at address 224

81 Figure RAM RAM ROM 8-port I/O chip

82 Figure.47 Device 64 8 RAM 32 8 RAM 8-port I/O 32 8 ROM Minimum address Maximum address General address xx xxxx x xxxx xxx x xxxx

83 Figure.48 A A A2 A3 A4 A5 A6 A7 CS A CS A CS A CS A A A A A A2 A2 A2 A2 A3 A3 A3 A4 A4 A4 A bit RAM 32 8 bit RAM 8-port I/O 32 8 bit ROM

84 Partial address decoding xx xxxx, 64 8 bit RAM x xxxx, 32 8 bit RAM xxx, 8-port I/O chip x xxxx, 32 8 bit ROM

85 Figure.49 A A A2 A3 A4 A5 A6 A7 CS A CS A CS A CS A A A A A A2 A2 A2 A2 A3 A3 A3 A4 A4 A4 A bit RAM 32 8 bit RAM 8-port I/O 32 8 bit ROM

86 Figure RAM ROM RAM 8-port I/O chip

87 Two-port register bank Implementation of the registers (accumulator, index register, etc.) in the Pep/8 CPU The data buses are unidirectional instead of bidirectional There are two output ports instead of one

88 LoadCk C 5 B 5 A 5 A 2 X 3 4 SP 5 6 PC 7 8 IR 9 T 2 T2 3 4 T3 5 6 T4 7 8 T5 9 2 T x x x2 x3 x4 x8 xfa xfc xfe xff M M M M M5 3 CPU registers CBus ABus BBus Figure.5

89 Figure.52 C LoadCk 5 5 A 5 32 decoder input multiplexers ABus 5 B 8 32-input multiplexers BBus CBus

90 Figure.53

91 Figure.54

92 Figure.55

Combinational vs Sequential

Combinational vs Sequential inputs X Combinational Circuits outputs Z A combinational circuit: At any time, outputs depends only on inputs Changing inputs changes outputs No regard for previous inputs