Part II. Chapter2: Synchronous Sequential Logic

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1 課程名稱 : 數位系統設計導論 P-/77 Part II Chapter2: Synchronous Sequential Logic 教師 : 郭峻因教授 INSTRUCTOR: Prof. Jiun-In Guo jiguo@cs.ccu.edu.tw

2 課程名稱 : 數位系統設計導論 P-2/77 Special thanks to Prof. CHING-LING SU for providing this course materials!!!!

3 Chapter 5 P-3/77 Chapter 5 Synchronous Sequential Logic

4 Outline P-4/77 5. Sequential Logics 5.2 Latches 5.3 Flip-Flops 5.4 Analysis of Clocked Sequential Circuits 5.5 HDL for Sequential Circuits 5.6 State Reduction and Assignment 5.7 Design Procedure

5 5. Sequential Circuits P-5/77 5. Sequential Logics 5.2 Latches 5.3 Flip-Flops 5.4 Analysis of Clocked Sequential Circuits 5.5 HDL for Sequential Circuits 5.6 State Reduction and Assignment 5.7 Design Procedure

6 5. Sequential Circuits P-6/77 Combinational and Sequential Circuits Logic Circuit Combinational Circuit: Output only depends on the present combination of inputs Specified by a set of Boolean Functions Sequential Circuit: Output depends on the input and the state of the storage (past inputs)

7 5. Sequential Circuits P-7/77 Block Diagram of Sequential Circuits The present state and inputs determine the output and the next state. Inputs Combinational Circuits Next State Memory Elements Outputs Feedback Path Present State

8 5. Sequential Circuits P-8/77 Classifications of Sequential Circuits Sequential Circuit Synchronous Sequential Circuit: The behavior can be defined form the knowledge of its signals at discrete instants of time. Asynchronous Sequential Circuit: The behavior depends on the input signals at any time instant of time and the order in which the inputs change. (Refer to Chapter 9)

9 5. Sequential Circuits P-9/77 Synchronous Clocked Sequential Circuits Clocked Sequential Circuit Inputs Combinational Circuits Flip-Flops Outputs Clock Generator Periodic Clock Pulse Storing bit information

10 5.2 Latches P-0/77 5. Sequential Logics 5.2 Latches 5.3 Flip-Flops 5.4 Analysis of Clocked Sequential Circuits 5.5 HDL for Sequential Circuits 5.6 State Reduction and Assignment 5.7 Design Procedure

11 5.2 Latches P-/77 Flip-Flop Flop A Flip-flop circuit can maintain a binary state indefinitely until directed by an input signal to switch states.

12 5.2 Latches P-2/77 R (reset) S (set) Logic Diagram SR Latch with NOR Gates Q Q Functional Table S R Q Q After S=, R=0 After S=0, R= R (reset) 0 Q R (reset) 0 Q S (set) 0 Q S (set) 0 0 Q R (reset) 0 Q R (reset) 0 0 Q S (set) 0 Q S (set) 0 Q

13 5.2 Latches P-3/77 S (set) R (reset) Logic Diagram SR Latch with NAND Gates Q Q Functional Table S R Q Q After S=, R=0 After S=0, R= S (set) 0 Q S (set) 0 Q R (reset) 0 Q R (reset) Q S (set) 0 Q S (set) Q R (reset) 0 Q R (reset) 0 Q

14 5.2 Latches P-4/77 SR Latch with Control Input S C R Logic Diagram Q Q Function Table C S R Next State 0 X X No Change 0 0 No Change 0 Q=0; Reset 0 Q=; Set Indeterminate S No Change Q S 0 No Change Q C 0 C R Q R 0 Q S Set 0 Q S 0 Reset 0 Q C C R 0 0 Q R 0 Q

15 5.2 Latches P-5/77 D Latch: Elimination the undesirable condition of the indeterminate state in SR latch

16 5.2 Latches P-6/77 Graphic Symbols for Latches SR Latch S SR Latch S R R D D Latch C

17 5.3 Flip-Flops Flops P-7/77 5. Sequential Logics 5.2 Latches 5.3 Flip-Flops 5.4 Analysis of Clocked Sequential Circuits 5.5 HDL for Sequential Circuits 5.6 State Reduction and Assignment 5.7 Design Procedure

18 5.3 Flip-Flops Flops P-8/77 Trigger: The change of the input control signal to switch the state of a latch or flip-flop Trigger Level Trigger: Latch Edge Trigger: Flip-flop

19 5.3 Flip-Flops Flops P-9/77 Problem of Level Trigger: During the period of level triggers, the feedback loops cause the unpredictable results. Inputs Combinational Circuits Flip-Flops Outputs Unpredictable Results Loops Clock Generator

20 5.3 Flip-Flops Flops P-20/77 Edge-Triggered D Flip-Flop Flop D X D C D Latch (Master) X D C D Latch (Slave) Q Clock Negative Edge Trigger Data Transfer

21 5.3 Flip-Flops Flops P-2/77 Positive-Edge Edge-Triggered D Flip-Flop Flop

22 5.3 Flip-Flops Flops P-22/77 Setup Time and Hold Time for Flip-Flop Flop Input D must be a stable data!! Clock Setup Time Input data D Hold Time

23 5.3 Flip-Flops Flops P-23/77 Graphic Symbols for D Flip-Flop Flop D D C Positive-Edge Triggered D FF C Negative-Edge Triggered D FF

24 5.3 Flip-Flops Flops P-24/77 Characteristic Table of D Flip-Flop Flop D Q(t+) 0 0 Reset Set Characteristic Table

25 5.3 Flip-Flops Flops P-25/77 JK Flip-Flop Flop J K D Q J C Clock C Q K Circuit Diagram Graphic Symbol J K D(t+) D = JQ + K Q 0 0 Q(t) No change 0 0 Reset 0 Set Q (t) Complement Characteristic Table

26 5.3 Flip-Flops Flops P-26/77 T (toggle) Flip-Flop Flop T D T J C C K T FF from D FF T FF from JK FF T Q(t+) D = T + Q = TQ + T Q 0 Q(t) No Change Q (t) Complement Characteristic Table T C Graphic Symbol

27 5.3 Flip-Flops Flops P-27/77 Characteristic Equations: The logical properties of a flip-flop as described in the characteristic table can be expressed also algebraically with a characteristic equation. D FF: Q(t+) = D JK FF: Q(t+) = JQ + K Q T FF: Q(t+) = T + Q = TQ + T Q

28 5.3 Flip-Flops Flops P-28/77 Direct Inputs (Asynchronous Inputs) Circuit Diagram Clock S R Q Q Clock 0 S R 0 0 Q Q D Reset D Direct Reset (Clear) 0 0 Data Graphic Symbol D Q Function Table R C D Q Q Clock C R Q 0 X X Reset

29 5.4 Analysis of Clocked Sequential Circuits P-29/77 5. Sequential Logics 5.2 Latches 5.3 Flip-Flops 5.4 Analysis of Clocked Sequential Circuits 5.5 HDL for Sequential Circuits 5.6 State Reduction and Assignment 5.7 Design Procedure

30 5.4 Analysis of Clocked Sequential Circuits P-30/77 State Equation (Transition Equation): State Equation (Transition Equation): A state equation (also called transition equation) specified the next state as a function of the present state and inputs.

31 5.4 Analysis of Clocked Sequential Circuits P-3/77 Example of Sequential Circuit x D A A(t+) = A(t)x(t) + B(t)x(t) B(t+) = A (t)x(t) C A A(t+) = Ax + Bx B(t+) = A x Clock D C B B y(t) = [A(t)+B(t)]x (t) y y = (A+B)x

32 5.4 Analysis of Clocked Sequential Circuits P-32/77 State Table (Transition Table) Table Consist of 4 sections:. Present State 2. Inputs 3. Next State 4. Outputs

33 5.4 Analysis of Clocked Sequential Circuits P-33/77 Example of State Table (Transition Table) Example State Table Depend on Circuit x D C A A Present Next State Input State Output A B x A B y Clock D C B B 2 3 Items y

34 5.4 Analysis of Clocked Sequential Circuits P-34/77 Example of State Table (Transition Table) Example Second Form of the State Table x D C A A Present State Next State Output x=0 x= x=0 x= AB AB AB y y Clock D C B B y

35 5.4 Analysis of Clocked Sequential Circuits P-35/77 State Diagram 0/0 00 0/ 0 /0 0/ 0/ 0 /0 /0 /0 Input/Output State Present State Next State Output x=0 x= x=0 x= AB AB AB y y

36 5.4 Analysis of Clocked Sequential Circuits P-36/77 Flip-Flop Flop Input Equations. The logic diagram of a sequential circuit consists of flipflops and gates. 2. The part of combination circuit that generates external outputs is described algebraically by a set of Boolean functions called output equations. 3. The part of the circuit that generates the inputs to flipflops is described algebraically by a set of Boolean functions called flip-flop input equations (sometimes called excitation equations). 4. The designer adopts the convention of using the flipflop input symbol to denote the input variable and subscript to designate the name of the flip-flop outputs.

37 5.4 Analysis of Clocked Sequential Circuits P-37/77 Example of Flip-Flop Flop Input Equations

38 5.4 Analysis of Clocked Sequential Circuits P-38/77 Analysis with D Flip-Flops Flops

39 5.4 Analysis of Clocked Sequential Circuits P-39/77 The next-state can be derived by following procedure. Determine the flip-flop equations in terms of the present state and input variables 2. List the binary values of each input equation 3. Use the corresponding flip-flop characteristic table to determine the next state values in the state table

40 5.4 Analysis of Clocked Sequential Circuits P-40/77 Analysis with JK Flip-Flops Flops

41 5.4 Analysis of Clocked Sequential Circuits P-4/77 Analysis with JK Flip-Flops Flops (Continued) Sequential Circuit with JK Flip-Flop Present Next Flip-Flop State Input State Inputs A B x A B J A K A J B K B

42 5.4 Analysis of Clocked Sequential Circuits P-42/77 The next-state can be obtained by evaluating the state equation from the characteristic equation. Determine the flip-flop equations in terms of the present state and input variables 2. Substitute the input equations into the flip-flop characteristic equation to obtain the state equation 3. Use the corresponding state equations to determine the next state values in the state table

43 5.4 Analysis of Clocked Sequential Circuits P-43/77 Analysis with JK Flip-Flops Flops (Continued) JK Flip-Flop Characteristic Equations A(t+) = JA + K A B(t+) = JB + K B A(t+) = BA + (Bx) A = A B + AB + Ax B(t+) = x B + (A + x ) B = B x + ABx + A Bx Flip-Flop Input Equations J A = B K A = Bx J B = x K B = A x + Ax = A x State Diagram

44 5.4 Analysis of Clocked Sequential Circuits P-44/77 Analysis with T Flip-Flops Flops

45 5.4 Analysis of Clocked Sequential Circuits P-45/77 Analysis with T Flip-Flops Flops (Continued) State Table Present Next State Input State Output AB x AB y State Diagram /0 0/0 / 0/0 0 0

46 5.4 Analysis of Clocked Sequential Circuits P-46/77 Mealy and Moore Models Model Classification of Sequential Circuits Mealy Model (Mealy FSM, Mealy Machine): The output is a function of both the present state and input. Moore Model (Moore FSM, Moore Machine): The output is a function of present state only. The output are synchronous with the clock.

47 5.4 Analysis of Clocked Sequential Circuits P-47/77 Example of Mealy Model x D A C A D B Clock C B y

48 5.4 Analysis of Clocked Sequential Circuits P-48/77 Example of Moore Model

49 5.5 HDL for Sequential Circuits P-49/77 5. Sequential Logics 5.2 Latches 5.3 Flip-Flops 5.4 Analysis of Clocked Sequential Circuits 5.5 HDL for Sequential Circuits 5.6 State Reduction and Assignment 5.7 Design Procedure

50 5.5 HDL for Sequential Circuits P-50/77 Referred to TA

51 5.6 State Reduction and Assignment P-5/77 5. Sequential Logics 5.2 Latches 5.3 Flip-Flops 5.4 Analysis of Clocked Sequential Circuits 5.5 HDL for Sequential Circuits 5.6 State Reduction and Assignment 5.7 Design Procedure

52 5.6 State Reduction and Assignment P-52/77 State Reduction of Sequential Circuits. State Reduction: Lower the requirement of flip-flop 2. m flip-flop produce 2 m states 3. The characteristic of a sequential circuit: inputoutput sequences (not the internal circuits)

53 5.6 State Reduction and Assignment P-53/77 Example of State Reduction

54 5.6 State Reduction and Assignment P-54/77 Example of State Reduction (Continued) State Table Next State Output Present State x=0 x= x=0 x= a a b 0 0 b c d 0 0 c a d 0 0 d e f 0 e a f 0 f g f 0 g a f 0 Equivalent State Removed State

55 5.6 State Reduction and Assignment P-55/77 Example of State Reduction (Continued) State Table Next State Output Present State x=0 x= x=0 x= a a b 0 0 b c d 0 0 c a d 0 0 d e f 0 e a f 0 f g f 0 g replaced by e

56 5.6 State Reduction and Assignment P-56/77 Example of State Reduction (Continued) State Table Next State Output Present State x=0 x= x=0 x= a a b 0 0 b c d 0 0 c a d 0 0 d e f 0 e a f 0 f e f 0 Equivalent State Removed State

57 5.6 State Reduction and Assignment P-57/77 Example of State Reduction (Continued) State Table Next State Output Present State x=0 x= x=0 x= a a b 0 0 b c d 0 0 c a d 0 0 d e f 0 e a f 0 f replaced by d

58 5.6 State Reduction and Assignment P-58/77 Example of State Reduction (Continued) State Table Next State Output Present State x=0 x= x=0 x= a a b 0 0 b c d 0 0 c a d 0 0 d e d 0 e a d 0

59 5.6 State Reduction and Assignment P-59/77 Example of State Reduction (Continued) State Diagram 0/0 Initial state a, I/O sequence: State a a b c d e d d e d e a Input Output c 0/0 a /0 0/0 0/0 b c 0/0 / d /0 /0 /

60 5.6 State Reduction and Assignment P-60/77 State Assignment

61 5.7 Design Procedure P-6/77 5. Sequential Logics 5.2 Latches 5.3 Flip-Flops 5.4 Analysis of Clocked Sequential Circuits 5.5 HDL for Sequential Circuits 5.6 State Reduction and Assignment 5.7 Design Procedure

62 5.7 Design Procedure P-62/77 Design Procedure for Synchronous Sequential Circuits. Derive a state diagram 2. Reduce the number of states if necessary 3. Assign binary values to the state 4. Obtain the binary-coded state table 5. Choose the type of flip-flops to be used 6. Derive the simplified flip-flop input equations and output equations 7. Draw the logic diagram

63 5.7 Design Procedure P-63/77 Design Example: Problem Description Design a circuit that detects three or more consecutive s in a string of bits coming through an input line. 0 0 S 0 /0 S /0 0 0 S 3 / S 2 /0

64 5.7 Design Procedure P-64/77 Synthesis Using D Flip-Flops Flops. Design by EDA Tools: Transfer the problem description into the synthesizable HDL Language and employ the synthesis tool to generate the circuit netlist (Reference to 5.6). 2. Design by hand: Next transparency

65 5.7 Design Procedure P-65/77 Assign Binary Code to the States S 0 S S 2 S 3 00 (AB) 0 (AB) 0 (AB) (AB)

66 5.7 Design Procedure P-66/77 List State Table with D FFs State Table Present Next State Input State Output AB x AB y m m m m m m m m 7

67 5.7 Design Procedure P-67/77 Find the Next State and Output Equations A(t+) = D A (A,B,x) = Σ (3,5,7) B(t+) = D B (A,B,x) = Σ (,5,7) y = (A,B,x) = Σ (6,7) D A = Ax + Bx D B = Ax + B x y = AB

68 5.7 Design Procedure P-68/77 Logic Simplification D A Bx A 00 B= 0 0 D B Bx A 00 B= A= A= x= D A = Ax + Bx x= D B = Ax + B x y Bx A 00 B= A= x= y = AB

69 5.7 Design Procedure P-69/77 Draw the Logic Diagram of Sequential Circuits Ax D A x Bx C B x D B Clock C B y

70 5.7 Design Procedure P-70/77 Excitation Tables A table lists the required inputs for a given change of state. Q(t) Q(t+) JK Flip-Flop J K Q(t+) 0 0 Q(t) No change 0 x 0 0 Reset 0 Set Q (t) Complement Characteristic Table Q(t) Q(t+) J K x 0 x 0 x x 0 Excitation Table

71 5.7 Design Procedure P-7/77 Excitation Tables (Continued) T Flip-Flop T Characteristic Table Q(t+) Excitation Table Q(t) Q(t+) T 0 Q(t) No Change Q (t) Complement

72 5.7 Design Procedure P-72/77 Synthesis Using JK Flip-Flops Flops State Table Present Next Flip-Flop State Input State Input AB x AB J A K A J B K B x 0 x x x x x x x x 0 0 x 0 x 0 x 0 x 0 x 0 00 x x

73 5.7 Design Procedure P-73/77 K-Map Logic Simplification

74 5.7 Design Procedure P-74/77 Draw the Sequential Circuits with JK FFs x Bx J A C Bx K A x J B C A + x K B Clock

75 5.7 Design Procedure P-75/77 Synthesis Using T Flip-Flops Flops Design Example: 3-bit Binary Counter Using T FFs. N-bit binary counter consists of n flip-flops 2. N-bit binary counter can count 0 to 2 n bit counter 0 to bit counter internal states 000 to

5.7 Design Procedure P-76/77 State Diagram and State Table of 3-bit 3 Binary Counter State Diagram State Table 00 000 Present State Next State

76 5.7 Design Procedure P-76/77 State Diagram and State Table of 3-bit 3 Binary Counter State Diagram State Table Present State Next State Flip-Flop Inputs A 2 A A 0 A 2 A A 0 T A2 T A T A Refer to T-FF Excitation Table

77 5.7 Design Procedure P-77/77 K-Map Logic Simplification for 3-bit 3 Binary Counter T A2 = A A 0 T A = A 0 A A 0 A 2 00 A 0 0 A A 0 A 2 00 A A 2 = A 2 = T A0 = A 0 A 0 A A 0 A A 0 0 A 2 = A 0

78 5.7 Design Procedure P-78/77 Draw the 3-bit 3 Binary Counter Circuits with T FFs A 2 A A 0 C T C T C T Clock

79 Exercise P-79/77 Problem set 5-2, 5-6, 5-7, 5-9, 5-2, 5-6, 5-9, 5-20, 5-30 Deadline 2005/5/9

Synchronous Sequential Logic. Chapter 5

Synchronous Sequential Logic. Chapter 5 Synchronous Sequential Logic Chapter 5 5-1 Introduction Combinational circuits contains no memory elements the outputs depends on the inputs Synchronous Sequential Logic 5-2 5-2 Sequential Circuits Sequential