Digital Logic Design I
|
|
- Sabrina Armstrong
- 6 years ago
- Views:
Transcription
1 Digital Logic Design I Synchronous Sequential Logic Mustafa Kemal Uyguroğlu
2 Sequential Circuits Asynchronous Inputs Combinational Circuit Memory Elements Outputs Synchronous Inputs Combinational Circuit Outputs Clock Flip-flops
3 Latches SR Latch S R = R S Initial Value Eastern Mediterranean University 2
4 Latches SR Latch R S R = = S Eastern Mediterranean University 3
5 Latches SR Latch R S R = = S Eastern Mediterranean University 4
6 Latches SR Latch R S R = = = S Eastern Mediterranean University 5
7 Latches SR Latch R S R = = = S Eastern Mediterranean University 6
8 Latches SR Latch R S R = = = = S Eastern Mediterranean University 7
9 Latches SR Latch R S R = = = = S Eastern Mediterranean University 8
10 Latches SR Latch R S S R = = = = = Eastern Mediterranean University 9
11 Latches SR Latch R S S R = = No change Reset Set Invalid S R S R = = Invalid Set Reset No change Eastern Mediterranean University
12 Latches SR Latch R S S R = = No change Reset Set Invalid S R S R = = Invalid Set Reset No change Eastern Mediterranean University
13 Controlled Latches SR Latch with Control Input R R S S C C S S R R C S R x x = No change No change Reset Set Invalid Eastern Mediterranean University 2
14 Controlled Latches D Latch (D = Data) Timing Diagram D C S C D R C D x No change Reset Set t Output may change Eastern Mediterranean University 3
15 Controlled Latches D Latch (D = Data) Timing Diagram D C S C D R C D x No change Reset Set Output may change Eastern Mediterranean University 4
16 Flip-Flops Controlled latches are level-triggered C Flip-Flops are edge-triggered CLK Positive Edge CLK Negative Edge Eastern Mediterranean University 5
17 Flip-Flops Master-Slave D Flip-Flop D D C D Latch (Master) D C D Latch (Slave) CLK CLK Master Slave Looks like it is negative edge-triggered D Master Slave Eastern Mediterranean University 6
18 Flip-Flops Edge-Triggered D Flip-Flop D CLK D Positive Edge D Negative Edge Eastern Mediterranean University 7
19 Flip-Flops JK Flip-Flop J K D CLK D = J + K J K Eastern Mediterranean University 8
20 Flip-Flops T Flip-Flop T J T D K D = J + K D = T + T = T T Eastern Mediterranean University 9
21 Flip-Flop Characteristic Tables D D (t+) Reset Set J K J K (t+) (t) (t) No change Reset Set Toggle T T (t+) (t) (t) No change Toggle Eastern Mediterranean University 2
22 Flip-Flop Characteristic Equations D D (t+) (t+) = D J K J K (t+) (t) (t) (t+) = J + K T T (t+) (t) (t) (t+) = T Eastern Mediterranean University 2
23 Flip-Flop Characteristic Equations Analysis / Derivation J K J K (t) (t+) No change Reset Set Toggle Eastern Mediterranean University 22
24 Flip-Flop Characteristic Equations Analysis / Derivation J K J K (t) (t+) No change Reset Set Toggle Eastern Mediterranean University 23
25 Flip-Flop Characteristic Equations Analysis / Derivation J K J K (t) (t+) No change Reset Set Toggle Eastern Mediterranean University 24
26 Flip-Flop Characteristic Equations Analysis / Derivation J K J K (t) (t+) No change Reset Set Toggle Eastern Mediterranean University 25
27 Flip-Flop Characteristic Equations Analysis / Derivation J K J K (t) (t+) (t+) = J + K K J Eastern Mediterranean University 26
28 Flip-Flops with Direct Inputs Asynchronous Reset D R D CLK (t+) x x R Reset Eastern Mediterranean University 27
29 Flip-Flops with Direct Inputs Asynchronous Reset D R R D CLK (t+) x x Reset Eastern Mediterranean University 28
30 Flip-Flops with Direct Inputs Asynchronous Preset and Clear Preset PR D PR CLR D CLK (t+) x x Reset CLR Eastern Mediterranean University 29
31 Flip-Flops with Direct Inputs Asynchronous Preset and Clear Preset Reset PR D CLR PR CLR D CLK (t+) x x x x Eastern Mediterranean University 3
32 Flip-Flops with Direct Inputs Asynchronous Preset and Clear Preset Reset PR D CLR PR CLR D CLK (t+) x x x x Eastern Mediterranean University 3
33 Analysis of Clocked Sequential Circuits The State State = Values of all Flip-Flops Example x D A A B = D B CLK y Eastern Mediterranean University 32
34 Analysis of Clocked Sequential Circuits State Equations A(t+) = D A x D A = A(t) x(t)+b(t) x(t) = A x + B x D B B(t+) = D B = A (t) x(t) CLK = A x y y(t) = [A(t)+ B(t)] x (t) = (A + B) x Eastern Mediterranean University 33
35 Analysis of Clocked Sequential Circuits State Table (Transition Table) Present State Input Next State Output A B x A B y t t+ t x CLK A(t+) = A x + B x B(t+) = A x y(t) = (A + B) x Eastern Mediterranean University 34 D D A B y
36 Analysis of Clocked Sequential Circuits State Table (Transition Table) Present State Next State Output x = x = x = x = A B A B A B y y x CLK D D A B y t t+ t A(t+) = A x + B x B(t+) = A x y(t) = (A + B) x Eastern Mediterranean University 35
37 Analysis of Clocked Sequential Circuits State Diagram AB input/output / / / Present State Next State Output x = x = x = x = A B A B A B y y / / / / x D A D B / CLK y Eastern Mediterranean University 36
38 Analysis of Clocked Sequential Circuits D Flip-Flops Example: Present State Input Next State A x y A x y CLK Eastern Mediterranean University 37 D A(t+) = D A = A x y,,,, A
39 Analysis of Clocked Sequential Circuits JK Flip-Flops J A Example: x K Present State I/P Next State Flip-Flop Inputs J B A B x A B J A K A J B K B CLK J A = B K A = B x J B = x K B = A x A(t+) = J A A + K A A = A B + AB + Ax B(t+) = J B B + K B B = B x + ABx + A Bx Eastern Mediterranean University 38 K
40 Analysis of Clocked Sequential Circuits JK Flip-Flops J A Example: x K Present Next Flip-Flop I/P State State Inputs A B x A B J A K A J B K B CLK Eastern Mediterranean University 39 J K B
41 Analysis of Clocked Sequential Circuits T Flip-Flops x T A y Example: Present Next F.F I/P State State Inputs O/P A B x A B T A T B y CLK T A = B x y = A B T B = x A(t+) = T A A + T A A = AB + Ax + A Bx B(t+) = T B B + T B B = x B Eastern Mediterranean University 4 T R R Reset B
42 Analysis of Clocked Sequential Circuits T Flip-Flops x T A y Example: Present Next F.F I/P State State Inputs O/P A B x A B T A T B y / / / CLK Eastern Mediterranean University 4 T R R Reset / B / / / /
43 Mealy and Moore Models The Mealy model: the outputs are functions of both the present state and inputs (Fig. 5-5). The outputs may change if the inputs change during the clock pulse period. The outputs may have momentary false values unless the inputs are synchronized with the clocks. The Moore model: the outputs are functions of the present state only (Fig. 5-2). The outputs are synchronous with the clocks. Eastern Mediterranean University 42
44 Mealy and Moore Models Fig. 5.2 Block diagram of Mealy and Moore state machine Eastern Mediterranean University 43
45 Mealy and Moore Models Present State Mealy I/P Next State O/P A B x A B y Present State Moore I/P Next State O/P A B x A B y For the same state, the output changes with the input For the same state, the output does not change with the input Eastern Mediterranean University 44
46 Moore State Diagram State / Output / / / / Eastern Mediterranean University 45
47 State Reduction and Assignment State Reduction Reductions on the number of flip-flops and the number of gates. A reduction in the number of states may result in a reduction in the number of flip-flops. An example state diagram showing in Fig Fig State diagram Eastern Mediterranean University 46
48 State Reduction State: a a b c d e f f g f g a Input: Output: Only the input-output sequences are important. Two circuits are equivalent Have identical outputs for all input sequences; The number of states is not important. Fig State diagram Eastern Mediterranean University 47
49 Equivalent states Two states are said to be equivalent For each member of the set of inputs, they give exactly the same output and send the circuit to the same state or to an equivalent state. One of them can be removed. Eastern Mediterranean University 48
50 Reducing the state table e = g (remove g); d = f (remove f); Eastern Mediterranean University 49
51 The reduced finite state machine State: a a b c d e d d e d e a Input: Output: Eastern Mediterranean University 5
52 The checking of each pair of states for possible equivalence can be done systematically using Implication Table. The unused states are treated as don't-care condition fewer combinational gates. Fig Reduced State diagram Eastern Mediterranean University 5
53 Implication Table The state-reduction procedure for completely specified state tables is based on the algorithm that two states in a state table can be combined into one if they can be shown to be equivalent. There are occasions when a pair of states do not have the same next states, but, nonetheless, go to equivalent next states. Consider the following state table: (a, b) imply (c, d) and (c, d) imply (a, b). Both pairs of states are equivalent; i.e., a and b are equivalent as well as c and d. Eastern Mediterranean University 52
54 Implication Table The checking of each pair of states for possible equivalence in a table with a large number of states can be done systematically by means of an implication table. This a chart that consists of squares, one for every possible pair of states, that provide spaces for listing any possible implied states. Consider the following state table: Eastern Mediterranean University 53
55 Implication Table The implication table is: Eastern Mediterranean University 54
56 Implication Table On the left side along the vertical are listed all the states defined in the state table except the last, and across the bottom horizontally are listed all the states except the last. The states that are not equivalent are marked with a x in the corresponding square, whereas their equivalence is recorded with a. Some of the squares have entries of implied states that must be further investigated to determine whether they are equivalent or not. The step-by-step procedure of filling in the squares is as follows:. Place a cross in any square corresponding to a pair of states whose outputs are not equal for every input. 2. Enter in the remaining squares the pairs of states that are implied by the pair of states representing the squares. We do that by starting from the top square in the left column and going down and then proceeding with the next column to the right. Eastern Mediterranean University 55
57 Implication Table 3. Make successive passes through the table to determine whether any additional squares should be marked with a x. A square in the table is crossed out if it contains at least one implied pair that is not equivalent. 4. Finally, all the squares that have no crosses are recorded with check marks. The equivalent states are: (a, b), (d, e), (d, g), (e, g). We now combine pairs of states into larger groups of equivalent states. The last three pairs can be combined into a set of three equivalent states (d, e,g) because each one of the states in the group is equivalent to the other two. The final partition of these states consists of the equivalent states found from the implication table, together with all the remaining states in the state table that are not equivalent to any other state: The reduced state table is: (a, b) (c) (d, e, g) (f) Eastern Mediterranean University 56
58 Implication Table Eastern Mediterranean University 57
59 State Assignment State Assignment To minimize the cost of the combinational circuits. Three possible binary state assignments. (m states need n-bits, where 2 n > m) Eastern Mediterranean University 58
60 Any binary number assignment is satisfactory as long as each state is assigned a unique number. Use binary assignment. Eastern Mediterranean University 59
61 Design Procedure Design Procedure for sequential circuit The word description of the circuit behavior to get a state diagram; State reduction if necessary; Assign binary values to the states; Obtain the binary-coded state table; Choose the type of flip-flops; Derive the simplified flip-flop input equations and output equations; Draw the logic diagram; Eastern Mediterranean University 6
62 Design of Clocked Sequential Circuits Example: Detect 3 or more consecutive s S / S / S 3 / S 2 / State A B S S S 2 S 3 Eastern Mediterranean University 6
63 Design of Clocked Sequential Circuits Example: Detect 3 or more consecutive s Present State Input Next State Output A B x A B y S / S / S 3 / S 2 / Eastern Mediterranean University 62
64 Design of Clocked Sequential Circuits Example: Detect 3 or more consecutive s Present State Input Next State Output A B x A B y Synthesis using D Flip-Flops A(t+) = D A (A, B, x) = (3, 5, 7) B(t+) = D B (A, B, x) = (, 5, 7) y (A, B, x) = (6, 7) Eastern Mediterranean University 63
65 Design of Clocked Sequential Circuits with D F.F. Example: Detect 3 or more consecutive s Synthesis using D Flip-Flops D A (A, B, x) = (3, 5, 7) = A x + B x D B (A, B, x) = (, 5, 7) = A x + B x y (A, B, x) = (6, 7) = A B B A x B A x Eastern Mediterranean University 64 B A x
66 Design of Clocked Sequential Circuits with D F.F. Example: Detect 3 or more consecutive s Synthesis using D Flip-Flops D A = A x + B x D B = A x + B x y = A B x D A y D B CLK Eastern Mediterranean University 65
67 Flip-Flop Excitation Tables Present State Next State (t) (t+) F.F. Input D Present State Next State F.F. Input (t) (t+) J K x x x x (No change) (Reset) (Set) (Toggle) (Reset) (Toggle) (No change) (Set) (t) (t+) T Eastern Mediterranean University 66
68 Design of Clocked Sequential Circuits with JK F.F. Example: Detect 3 or more consecutive s Present State Input Next State Flip-Flop Inputs A B x A B J A K A J B K B x x x x x x x x x x x x x x x x Synthesis using JK F.F. J A (A, B, x) = (3) d JA (A, B, x) = (4,5,6,7) K A (A, B, x) = (4, 6) d KA (A, B, x) = (,,2,3) J B (A, B, x) = (, 5) d JB (A, B, x) = (2,3,6,7) K B (A, B, x) = (2, 3, 6) d KB (A, B, x) = (,,4,5) Eastern Mediterranean University 67
69 Design of Clocked Sequential Circuits with JK F.F. Example: Detect 3 or more consecutive s Synthesis using JK Flip-Flops x J A = B x K A = x J B = x K B = A + x J A K y J B B A x x x x x B x x A x x x B x x x x A x B x x A x x x K CLK Eastern Mediterranean University 68
70 Design of Clocked Sequential Circuits with T F.F. Example: Detect 3 or more consecutive s Present State Input Next State F.F. Input A B x A B T A T B Synthesis using T Flip-Flops T A (A, B, x) = (3, 4, 6) T B (A, B, x) = (, 2, 3, 5, 6) Eastern Mediterranean University 69
71 Design of Clocked Sequential Circuits with T F.F. Example: Detect 3 or more consecutive s Synthesis using T Flip-Flops T A = A x + A B x T B = A B + B x x T A y B B T B A x A x CLK Eastern Mediterranean University 7
Sequential Logic Circuits
Sequential Logic Circuits By Dr. M. Hebaishy Digital Logic Design Ch- Rem.!) Types of Logic Circuits Combinational Logic Memoryless Outputs determined by current values of inputs Sequential Logic Has memory
More informationSynchronous Sequential Logic. Chapter 5
Synchronous Sequential Logic Chapter 5 5-1 Introduction Combinational circuits contains no memory elements the outputs depends on the inputs Synchronous Sequential Logic 5-2 5-2 Sequential Circuits Sequential
More informationChapter 5: Synchronous Sequential Logic
Chapter 5: Synchronous Sequential Logic NCNU_2016_DD_5_1 Digital systems may contain memory for storing information. Combinational circuits contains no memory elements the outputs depends only on the inputs
More informationSynchronous Sequential Logic
Synchronous Sequential Logic ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2012 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines Sequential
More informationB.Tech CSE Sem. 3 15CS202 DIGITAL SYSTEM DESIGN (Regulations 2015) UNIT -IV
B.Tech CSE Sem. 3 5CS22 DIGITAL SYSTEM DESIGN (Regulations 25) UNIT -IV SYNCHRONOUS SEQUENTIAL CIRCUITS OUTLINE FlipFlops SR,D,JK,T Analysis of Synchronous Sequential Circuit State Reduction and Assignment
More informationSynchronous Sequential Logic
Synchronous Sequential Logic ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines Sequential
More informationPart II. Chapter2: Synchronous Sequential Logic
課程名稱 : 數位系統設計導論 P-/77 Part II Chapter2: Synchronous Sequential Logic 教師 : 郭峻因教授 INSTRUCTOR: Prof. Jiun-In Guo E-mail: jiguo@cs.ccu.edu.tw 課程名稱 : 數位系統設計導論 P-2/77 Special thanks to Prof. CHING-LING SU for
More informationLecture 11: Synchronous Sequential Logic
Lecture 11: Synchronous Sequential Logic Syed M. Mahmud, Ph.D ECE Department Wayne State University Aby K George, ECE Department, Wayne State University Contents Characteristic equations Analysis of clocked
More informationDigital Design, Kyung Hee Univ. Chapter 5. Synchronous Sequential Logic
Chapter 5. Synchronous Sequential Logic 1 5.1 Introduction Electronic products: ability to send, receive, store, retrieve, and process information in binary format Dependence on past values of inputs Sequential
More informationSynchronous Sequential Logic
MEC520 디지털공학 Synchronous Sequential Logic Jee-Hwan Ryu School of Mechanical Engineering Sequential Circuits Outputs are function of inputs and present states Present states are supplied by memory elements
More informationDigital Logic Design Sequential Circuits. Dr. Basem ElHalawany
Digital Logic Design Sequential Circuits Dr. Basem ElHalawany Combinational vs Sequential inputs X Combinational Circuits outputs Z A combinational circuit: At any time, outputs depends only on inputs
More informationUNIT III. Combinational Circuit- Block Diagram. Sequential Circuit- Block Diagram
UNIT III INTRODUCTION In combinational logic circuits, the outputs at any instant of time depend only on the input signals present at that time. For a change in input, the output occurs immediately. Combinational
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 8 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
More informationSequential Circuits. Output depends only and immediately on the inputs Have no memory (dependence on past values of the inputs)
Sequential Circuits Combinational circuits Output depends only and immediately on the inputs Have no memory (dependence on past values of the inputs) Sequential circuits Combination circuits with memory
More informationChapter 5 Synchronous Sequential Logic
Chapter 5 Synchronous Sequential Logic Chih-Tsun Huang ( 黃稚存 ) http://nthucad.cs.nthu.edu.tw/~cthuang/ Department of Computer Science National Tsing Hua University Outline Introduction Storage Elements:
More informationChapter 5 Synchronous Sequential Logic
EEA051 - Digital Logic 數位邏輯 Chapter 5 Synchronous Sequential Logic 吳俊興國立高雄大學資訊工程學系 December 2005 Chapter 5 Synchronous Sequential Logic 5-1 Sequential Circuits 5-2 Latches 5-3 Flip-Flops 5-4 Analysis of
More informationNH 67, Karur Trichy Highways, Puliyur C.F, Karur District UNIT-III SEQUENTIAL CIRCUITS
NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF ELETRONICS AND COMMUNICATION ENGINEERING COURSE NOTES SUBJECT: DIGITAL ELECTRONICS CLASS: II YEAR ECE SUBJECT CODE: EC2203
More informationOther Flip-Flops. Lecture 27 1
Other Flip-Flops Other types of flip-flops can be constructed by using the D flip-flop and external logic. Two flip-flops less widely used in the design of digital systems are the JK and T flip-flops.
More informationChapter. Synchronous Sequential Circuits
Chapter 5 Synchronous Sequential Circuits Logic Circuits- Review Logic Circuits 2 Combinational Circuits Consists of logic gates whose outputs are determined from the current combination of inputs. Performs
More informationLATCHES & FLIP-FLOP. Chapter 7
LATCHES & FLIP-FLOP Chapter 7 INTRODUCTION Latch and flip flops are categorized as bistable devices which have two stable states,called SET and RESET. They can retain either of this states indefinitely
More informationEMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP
EMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP 1 Chapter Overview Latches Gated Latches Edge-triggered flip-flops Master-slave flip-flops Flip-flop operating characteristics Flip-flop applications
More informationMC9211 Computer Organization
MC9211 Computer Organization Unit 2 : Combinational and Sequential Circuits Lesson2 : Sequential Circuits (KSB) (MCA) (2009-12/ODD) (2009-10/1 A&B) Coverage Lesson2 Outlines the formal procedures for the
More information`COEN 312 DIGITAL SYSTEMS DESIGN - LECTURE NOTES Concordia University
`OEN 32 IGITL SYSTEMS ESIGN - LETURE NOTES oncordia University hapter 5: Synchronous Sequential Logic NOTE: For more eamples and detailed description of the material in the lecture notes, please refer
More informationRS flip-flop using NOR gate
RS flip-flop using NOR gate Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two
More informationChapter 5. Introduction
Chapter 5 Synchronous Sequential Logic Chapter 5 Introduction Circuits require memory to store intermediate data Sequential circuits use a periodic signal to determine when to store values. A clock signal
More informationChapter 5 Sequential Circuits
Logic and omputer Design Fundamentals hapter 5 Sequential ircuits Part 1 Storage Elements and Sequential ircuit Analysis harles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active
More informationNH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN
NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT 4 SYNCHRONOUS SEQUENTIAL LOGIC Sequential circuits
More informationDigital Circuit And Logic Design I. Lecture 8
Digital Circuit And Logic Design I Lecture 8 Outline Sequential Logic Design Principles (1) 1. Introduction 2. Latch and Flip-flops 3. Clocked Synchronous State-Machine Analysis Panupong Sornkhom, 2005/2
More informationDigital Circuit And Logic Design I
Digital Circuit And Logic Design I Lecture 8 Outline Sequential Logic Design Principles (1) 1. Introduction 2. Latch and Flip-flops 3. Clocked Synchronous State-Machine Panupong Sornkhom, 2005/2 2 1 Sequential
More informationUnit 11. Latches and Flip-Flops
Unit 11 Latches and Flip-Flops 1 Combinational Circuits A combinational circuit consists of logic gates whose outputs, at any time, are determined by combining the values of the inputs. For n input variables,
More informationECE 25 Introduction to Digital Design. Chapter 5 Sequential Circuits ( ) Part 1 Storage Elements and Sequential Circuit Analysis
EE 25 Introduction to igital esign hapter 5 Sequential ircuits (5.1-5.4) Part 1 Storage Elements and Sequential ircuit Analysis Logic and omputer esign Fundamentals harles Kime & Thomas Kaminski 2008 Pearson
More informationSequential Design Basics
Sequential Design Basics Lecture 2 topics A review of devices that hold state A review of Latches A review of Flip-Flops Unit of text Set-Reset Latch/Flip-Flops/D latch/ Edge triggered D Flip-Flop 8/22/22
More informationChapter 5 Synchronous Sequential Logic
Chapter 5 Synchronous Sequential Logic Sequential Circuits Latches and Flip-Flops Analysis of Clocked Sequential Circuits HDL Optimization Design Procedure Sequential Circuits Various definitions Combinational
More informationFlip-Flops. Because of this the state of the latch may keep changing in circuits with feedback as long as the clock pulse remains active.
Flip-Flops Objectives The objectives of this lesson are to study: 1. Latches versus Flip-Flops 2. Master-Slave Flip-Flops 3. Timing Analysis of Master-Slave Flip-Flops 4. Different Types of Master-Slave
More informationCSE Latches and Flip-flops Dr. Izadi. NOR gate property: A B Z Cross coupled NOR gates: S M S R Q M
CSE-4523 Latches and Flip-flops Dr. Izadi NOR gate property: A B Z A B Z Cross coupled NOR gates: S M S R M R S M R S R S R M S S M R R S ' Gate R Gate S R S G R S R (t+) S G R Flip_flops:. S-R flip-flop
More informationEET2411 DIGITAL ELECTRONICS
5-8 Clocked D Flip-FlopFlop One data input. The output changes to the value of the input at either the positive going or negative going clock trigger. May be implemented with a J-K FF by tying the J input
More informationCombinational / Sequential Logic
Digital Circuit Design and Language Combinational / Sequential Logic Chang, Ik Joon Kyunghee University Combinational Logic + The outputs are determined by the present inputs + Consist of input/output
More informationChapter 8 Sequential Circuits
Philadelphia University Faculty of Information Technology Department of Computer Science Computer Logic Design By 1 Chapter 8 Sequential Circuits 1 Classification of Combinational Logic 3 Sequential circuits
More informationDigital Circuits ECS 371
igital Circuits ECS 371 r. Prapun Suksompong prapun@siit.tu.ac.th Lecture 17 Office Hours: BK 3601-7 Monday 9:00-10:30, 1:30-3:30 Tuesday 10:30-11:30 1 Announcement Reading Assignment: Chapter 7: 7-1,
More informationDr.Mohamed Elmahdy Winter 2015 Eng.Yasmin Mohamed. Problem Set 6. Analysis and Design of Clocked Sequential Circuits. Discussion: 7/11/ /11/2015
Dr. Elmahdy Winter 2015 Problem Set 6 Analysis and Design of Clocked Sequential Circuits Discussion: 7/11/2015 17/11/2015 *Exercise 6-1: (Problem 5.10) A sequential circuit has two JK flip-flops A and
More informationEngr354: Digital Logic Circuits
Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flip-flops;
More informationProblems with D-Latch
Problems with -Latch If changes while is true, the new value of will appear at the output. The latch is transparent. If the stored value can change state more than once during a single clock pulse, the
More informationFinal Exam review: chapter 4 and 5. Supplement 3 and 4
Final Exam review: chapter 4 and 5. Supplement 3 and 4 1. A new type of synchronous flip-flop has the following characteristic table. Find the corresponding excitation table with don t cares used as much
More information2 Sequential Circuits
2 2.1 State Diagrams and General Form 0/0 1/0 Start State 0 /0 1/1 State 1 /1 0/1 State Diagram of a Change Detector ( Mealy-machine). The output Y assumes 1 whenever the input X has changed. Otherwise
More informationLogic Design II (17.342) Spring Lecture Outline
Logic Design II (17.342) Spring 2012 Lecture Outline Class # 05 February 23, 2012 Dohn Bowden 1 Today s Lecture Analysis of Clocked Sequential Circuits Chapter 13 2 Course Admin 3 Administrative Admin
More informationChapter 6. Flip-Flops and Simple Flip-Flop Applications
Chapter 6 Flip-Flops and Simple Flip-Flop Applications Basic bistable element It is a circuit having two stable conditions (states). It can be used to store binary symbols. J. C. Huang, 2004 Digital Logic
More informationChapter 3 Unit Combinational
EE 2: igital Logic ircuit esign r Radwan E Abdel-Aal, OE Logic and omputer esign Fundamentals hapter 3 Unit ombinational 4 Sequential Logic esign ircuits Part Implementation Technology and Logic esign
More informationRS flip-flop using NOR gate
RS flip-flop using NOR gate Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two
More informationExperiment 8 Introduction to Latches and Flip-Flops and registers
Experiment 8 Introduction to Latches and Flip-Flops and registers Introduction: The logic circuits that have been used until now were combinational logic circuits since the output of the device depends
More informationChapter 11 Latches and Flip-Flops
Chapter 11 Latches and Flip-Flops SKEE1223 igital Electronics Mun im/arif/izam FKE, Universiti Teknologi Malaysia ecember 8, 2015 Types of Logic Circuits Combinational logic: Output depends solely on the
More informationCHAPTER 4: Logic Circuits
CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits
More informationCHAPTER1: Digital Logic Circuits
CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits 1 Sequential Circuits Introduction Composed of a combinational circuit to which the memory elements are connected to form a feedback
More informationUnit 9 Latches and Flip-Flops. Dept. of Electrical and Computer Eng., NCTU 1
Unit 9 Latches and Flip-Flops Dept. of Electrical and Computer Eng., NCTU 1 9.1 Introduction Dept. of Electrical and Computer Eng., NCTU 2 What is the characteristic of sequential circuits in contrast
More informationWEEK 10. Sequential Circuits: Analysis and Design. Page 1
WEEK 10 Sequential Circuits: Analysis and Design Page 1 Analysis of Clocked (Synchronous) Sequential Circuits Now that we have flip-flops and the concept of memory in our circuit, we might want to determine
More informationCHAPTER 4: Logic Circuits
CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits
More informationCHAPTER 1 LATCHES & FLIP-FLOPS
CHAPTER 1 LATCHES & FLIP-FLOPS 1 Outcome After learning this chapter, student should be able to; Recognize the difference between latches and flipflops Analyze the operation of the flip flop Draw the output
More informationEECS150 - Digital Design Lecture 19 - Finite State Machines Revisited
EECS150 - Digital Design Lecture 19 - Finite State Machines Revisited April 2, 2013 John Wawrzynek Spring 2013 EECS150 - Lec19-fsm Page 1 Finite State Machines (FSMs) FSM circuits are a type of sequential
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 6 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter
More informationSequential Logic. E&CE 223 Digital Circuits and Systems (A. Kennings) Page 1
Sequential Logic E&CE 223 igital Circuits and Systems (A. Kennings) Page 1 Sequential Circuits Have considered only combinational circuits in which circuit outputs are determined entirely by current circuit
More informationThe reduction in the number of flip-flops in a sequential circuit is referred to as the state-reduction problem.
State Reduction The reduction in the number of flip-flops in a sequential circuit is referred to as the state-reduction problem. State-reduction algorithms are concerned with procedures for reducing the
More informationCHAPTER 6 COUNTERS & REGISTERS
CHAPTER 6 COUNTERS & REGISTERS 6.1 Asynchronous Counter 6.2 Synchronous Counter 6.3 State Machine 6.4 Basic Shift Register 6.5 Serial In/Serial Out Shift Register 6.6 Serial In/Parallel Out Shift Register
More informationDigital Fundamentals: A Systems Approach
Digital Fundamentals: A Systems Approach Counters Chapter 8 A System: Digital Clock Digital Clock: Counter Logic Diagram Digital Clock: Hours Counter & Decoders Finite State Machines Moore machine: One
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 7 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
More information10.1 Sequential logic circuits are a type of logic circuit where the output of the circuit depends not only on
CALIFORNIA STATE UNIVERSITY LOS ANGELES Department of Electrical and Computer Engineering EE-2449 Digital Logic Lab EXPERIMENT 10 INTRODUCTION TO SEQUENTIAL LOGIC EE 2449 Experiment 10 nwp & jgl 1/1/18
More information(CSC-3501) Lecture 7 (07 Feb 2008) Seung-Jong Park (Jay) CSC S.J. Park. Announcement
Seung-Jong Park (Jay) http://www.csc.lsu.edu/~sjpark Computer Architecture (CSC-3501) Lecture 7 (07 Feb 2008) 1 Announcement 2 1 Combinational vs. Sequential Logic Combinational Logic Memoryless Outputs
More informationLogic Design. Flip Flops, Registers and Counters
Logic Design Flip Flops, Registers and Counters Introduction Combinational circuits: value of each output depends only on the values of inputs Sequential Circuits: values of outputs depend on inputs and
More informationAnalysis of Clocked Sequential Circuits
Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Analysis of Clocked Sequential circuits State
More informationYEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING. EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall
YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall Objective: - Dealing with the operation of simple sequential devices. Learning invalid condition in
More informationModule -5 Sequential Logic Design
Module -5 Sequential Logic Design 5.1. Motivation: In digital circuit theory, sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals but on
More informationCourse Administration
EE 224: INTRODUCTION TO DIGITAL CIRCUITS & COMPUTER DESIGN Lecture 5: Sequential Logic - 2 Analysis of Clocked Sequential Systems 4/2/2 Avinash Kodi, kodi@ohio.edu Course Administration 2 Hw 2 due on today
More informationLogic and Computer Design Fundamentals. Chapter 7. Registers and Counters
Logic and Computer Design Fundamentals Chapter 7 Registers and Counters Registers Register a collection of binary storage elements In theory, a register is sequential logic which can be defined by a state
More informationECE 301 Digital Electronics
ECE 301 Digital Electronics Derivation of Flip-Flop Input Equations and State Assignment (Lecture #24) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,
More informationSynchronous Sequential Logic
Synchronous Sequential Logic -A Sequential Circuit consists of a combinational circuit to which storage elements are connected to form a feedback path. The storage elements are devices capable of storing
More informationINTRODUCTION TO SEQUENTIAL CIRCUITS
NOTE: Explanation Refer Class Notes Digital Circuits(15EECC203) INTRODUCTION TO SEQUENTIAL CIRCUITS by Nagaraj Vannal, Asst.Professor, School of Electronics Engineering, K.L.E. Technological University,
More informationFlip-Flops and Sequential Circuit Design
Flip-Flops and Sequential Circuit Design ECE 52 Summer 29 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6
More informationFE REVIEW LOGIC. The AND gate. The OR gate A B AB A B A B 0 1 1
FE REVIEW LOGIC The AD gate f A, B AB The AD gates output will achieve its active state, ACTIVE HIGH, when BOTH of its inputs achieve their active state, ACTIVE E HIGH. A B AB f ( A, B) AB m (3) The OR
More informationCPS311 Lecture: Sequential Circuits
CPS311 Lecture: Sequential Circuits Last revised August 4, 2015 Objectives: 1. To introduce asynchronous and synchronous flip-flops (latches and pulsetriggered, plus asynchronous preset/clear) 2. To introduce
More informationThe word digital implies information in computers is represented by variables that take a limited number of discrete values.
Class Overview Cover hardware operation of digital computers. First, consider the various digital components used in the organization and design. Second, go through the necessary steps to design a basic
More informationCS T34-DIGITAL SYSTEM DESIGN Y2/S3
UNIT III Sequential Logic: Latches versus Flip Flops SR, D, JK, Master Slave Flip Flops Excitation table Conversion of Flip flops Counters: Asynchronous, synchronous, decade, presettable Shift Registers:
More informationUniversidad Carlos III de Madrid Digital Electronics Exercises
1. Complete the chronogram for the circuit given in the figure. inst7 NOT A INPUT VCC AND2 inst5 DFF D PRN Q CLRN inst XOR inst2 TFF PRN T Q CLRN inst8 OUTPUT OUTPUT Q Q1 CLK INPUT VCC CLEARN INPUT VCC
More informationSequential Logic and Clocked Circuits
Sequential Logic and Clocked Circuits Clock or Timing Device Input Variables State or Memory Element Combinational Logic Elements From combinational logic, we move on to sequential logic. Sequential logic
More informationD Latch (Transparent Latch)
D Latch (Transparent Latch) -One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that inputs S and R are never equal to 1 at the same time. This is done
More informationCounters
Counters A counter is the most versatile and useful subsystems in the digital system. A counter driven by a clock can be used to count the number of clock cycles. Since clock pulses occur at known intervals,
More informationUNIVERSITI TEKNOLOGI MALAYSIA
SULIT Faculty of Computing UNIVERSITI TEKNOLOGI MALAYSIA FINAL EXAMINATION SEMESTER I, 2016 / 2017 SUBJECT CODE : SUBJECT NAME : SECTION : TIME : DATE/DAY : VENUES : INSTRUCTIONS : Answer all questions
More informationUNIT IV. Sequential circuit
UNIT IV Sequential circuit Introduction In the previous session, we said that the output of a combinational circuit depends solely upon the input. The implication is that combinational circuits have no
More informationChapter 1: Switching Algebra Chapter 2: Logical Levels, Timing & Delays. Introduction to latches Chapter 9: Binary Arithmetic
12.12.216 Chapter 5 Flip Flops Dr.-ng. Stefan Werner /14 Table of content Chapter 1: Switching Algebra Chapter 2: Logical Levels, Timing & Delays Chapter 3: Karnaugh-Veitch-Maps Chapter 4: Combinational
More informationFigure 30.1a Timing diagram of the divide by 60 minutes/seconds counter
Digital Clock The timing diagram figure 30.1a shows the time interval t 6 to t 11 and t 19 to t 21. At time interval t 9 the units counter counts to 1001 (9) which is the terminal count of the 74x160 decade
More informationName Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers
EEE 304 Experiment No. 07 Name Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers Important: Submit your Prelab at the beginning of the lab. Prelab 1: Construct a S-R Latch and
More informationIntroduction to Sequential Circuits
Introduction to Sequential Circuits COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Introduction to Sequential Circuits Synchronous
More informationDepartment of Electrical and Computer Engineering Mid-Term Examination Winter 2012
1 McGill University Faculty of Engineering ECSE-221B Introduction to Computer Engineering Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012 Examiner: Rola Harmouche Date:
More informationLAB #4 SEQUENTIAL LOGIC CIRCUIT
LAB #4 SEQUENTIAL LOGIC CIRCUIT OBJECTIVES 1. To learn how basic sequential logic circuit works 2. To test and investigate the operation of various latch and flip flop circuits INTRODUCTIONS Sequential
More informationCOE 202: Digital Logic Design Sequential Circuits Part 1. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:
COE 202: Digital Logic Design Sequential Circuits Part 1 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Objectives Sequential Circuits Memory Elements Latches Flip-Flops Combinational
More informationReview of Flip-Flop. Divya Aggarwal. Student, Department of Physics and Astro-Physics, University of Delhi, New Delhi. their state.
pp. 4-9 Krishi Sanskriti Publications http://www.krishisanskriti.org/jbaer.html Review of Flip-Flop Divya Aggarwal Student, Department of Physics and Astro-Physics, University of Delhi, New Delhi Abstract:
More informationCMSC 313 Preview Slides
CMSC 33 Preview Slides These are draft slides. The actual slides presented in lecture may be different due to last minute changes, schedule slippage,... UMBC, CMSC33, Richard Chang CMSC
More informationSequential Circuits: Latches & Flip-Flops
Sequential Circuits: Latches & Flip-Flops Overview Storage Elements Latches SR, JK, D, and T Characteristic Tables, Characteristic Equations, Eecution Tables, and State Diagrams Standard Symbols Flip-Flops
More informationDigital Fundamentals. Lab 5 Latches & Flip-Flops CETT Name: Date:
Richland College School of Engineering & Technology Rev. 0 B. Donham Rev. 1 (7/2003) J. Horne Rev. 2 (1/2008) J. Bradbury Rev. 3 (7/2015) J. Bradbury Digital Fundamentals CETT 1425 Lab 5 Latches & Flip-Flops
More informationSynchronous Sequential Logic
Synchronous Sequential Logic Ranga Rodrigo August 2, 2009 1 Behavioral Modeling Behavioral modeling represents digital circuits at a functional and algorithmic level. It is used mostly to describe sequential
More informationChapter 2. Digital Circuits
Chapter 2. Digital Circuits Logic gates Flip-flops FF registers IC registers Data bus Encoders/Decoders Multiplexers Troubleshooting digital circuits Most contents of this chapter were covered in 88-217
More informationIT T35 Digital system desigm y - ii /s - iii
UNIT - III Sequential Logic I Sequential circuits: latches flip flops analysis of clocked sequential circuits state reduction and assignments Registers and Counters: Registers shift registers ripple counters
More informationSwitching Circuits & Logic Design, Fall Final Examination (1/13/2012, 3:30pm~5:20pm)
Switching Circuits & Logic Design, Fall 2011 Final Examination (1/13/2012, 3:30pm~5:20pm) Problem 1: (15 points) Consider a new FF with three inputs, S, R, and T. No more than one of these inputs can be
More information