Static Timing Analysis for Nanometer Designs

Transcription

1 J. Bhasker Rakesh Chadha Static Timing Analysis for Nanometer Designs A Practical Approach 4y Spri ringer

2 Contents Preface xv CHAPTER 1: Introduction / 1.1 Nanometer Designs What is Static Timing Analysis? Why Static Timing Analysis? 4 Crosstalk and Noise, Design Flow CMOS Digital Designs FPGA Designs Asynchronous Designs STA at Different Design Phases Limitations of Static Timing Analysis Power Considerations Reliability Considerations Outline of the Book 13 CHAPTER 2: STA Concepts CMOS Logic Design Basic MOS Structure CMOS Logic Gate Standard Cells Modeling of CMOS Cells Switching Waveform 23 v

3 2.4 Propagation Delay Slew of a Waveform Skew between Signals Timing Arcs and Unateness Min and Max Timing Paths Clock Domains Operating Conditions 39 CHAPTER 3: Standard Cell Library Pin Capacitance Timing Modeling Linear Timing Model Non-Linear Delay Model 47 Example of Non-Linear Delay Model Lookup, Threshold Specifications and Slew Derating Timing Models - Combinational Cells Delay and Slew Models 57 Positive or Negative Unate, General Combinational Block Timing Models - Sequential Cells Synchronous Checks: Setup and Hold 62 Example of Setup and Hold Checks, 62 Negative Values in Setup and Hold Checks, Asynchronous Checks 66 Recovery and Removal Checks, 66 Pulse Width Checks, 66 Example of Recovery, Removal and Pulse Width Checks, Propagation Delay State-Dependent Models 70 XOR, XNOR and Sequential Cells, Interface Timing Model for a Black Box Advanced Timing Modeling Receiver Pin Capacitance 76 Specifying Capacitance at the Pin Level, 77 Specifying Capacitance at the Timing Arc Level, Output Current 79

4 3.7.3 Models for Crosstalk Noise Analysis 80 DC Current, 82 Output Voltage, 83 Propagated Noise, 83 Noise Models for Two-Stage Cells, 84 Noise Models for Multi-stage and Sequential Cells, Other Noise Models Power Dissipation Modeling Active Power 88 Double Counting Clock Pin Power?, Leakage Power Other Attributes in Cell Library 94 Area Specification, 94 Function Specification, 95 SDF Condition, Characterization and Operating Conditions 96 What is the Process Variable?, Derating using K-factors Library Units 99 CHAPTER 4: Interconnect Parasitics RLC for Interconnect 102 T-model, 103 Pi-model, Wireload Models Interconnect Trees Specifying Wireload Models Representation of Extracted Parasitics Detailed Standard Parasitic Format Reduced Standard Parasitic Format Standard Parasitic Exchange Format Representing Coupling Capacitances Hierarchical Methodology 119 Block Replicated in Layout, Reducing Parasitics for Critical Nets 120 Reducing Interconnect Resistance, 120 Increasing Wire Spacing, 121 vii

5 Parasitics for Correlated Nets, 121 CHAPTER 5: Delay Calculation Overview Delay Calculation Basics Delay Calculation with Interconnect 125 Pre-layout Timing, 125 Post-layout Timing, Cell Delay using Effective Capacitance Interconnect Delay 131 Elmore Delay, 132 Higher Order Interconnect Delay Estimation, 134 Full Chip Delay Calculation, Slew Merging Different Slew Thresholds Different Voltage Domains Path Delay Calculation Combinational Path Delay Path to a Flip-flop 143 Input to Flip-flop Path, 143 Flip-flop to Flip-flop Path, Multiple Paths Slack Calculation 146 CHAPTER 6: Crosstalk and Noise Overview Crosstalk Glitch Analysis Basics Types of Glitches 152 Rise and Fall Glitches, 152 Overshoot and Undershoot Glitches, Glitch Thresholds and Propagation 153 DC Thresholds, 153 AC Thresholds, Noise Accumulation with Multiple Aggressors Aggressor Timing Correlation 160 Vlll

6 6.2.6 Aggressor Functional Correlation Crosstalk Delay Analysis Basics Positive and Negative Crosstalk Accumulation with Multiple Aggressors Aggressor Victim Timing Correlation Aggressor Victim Functional Correlation Timing Verification Using Crosstalk Delay Setup Analysis Hold Analysis Computational Complexity 175 Hierarchical Design and Analysis, 175 Filtering of Coupling Capacitances, Noise Avoidance Techniques 176 CHAPTER 7: Configuring the STA Environment What is the STA Environment? Specifying Clocks Clock Uncertainty Clock Latency Generated Clocks 190 Example of Master Clock at Clock Gating Cell Output, 194 Generated Clock using Edge and Edgeshift Options, 195 Generated Clock using Invert Option, 198 Clock Latency for Generated Clocks, 200 Typical Clock Generation Scenario, Constraining Input Paths Constraining Output Paths 205 Example A, 205 Example B, 206 Example C, Timing Path Groups Modeling of External Attributes Modeling Drive Strengths Modeling Capacitive Load Design Rule Checks 215 ix

7 7.9 Virtual Clocks Refining the Timing Analysis Specifying Inactive Signals Breaking Timing Arcs in Cells Point-to-Point Specification Path Segmentation 224 CHAPTER 8: Timing Verification Setup Timing Check Flip-flop to Flip-flop Path Inputto Flip-flop Path 237 Input Path with Actual Clock, Flip-flop to Output Path Input to Output Path Frequency Histogram Hold Timing Check Flip-flop to Flip-flop Path 252 Hold Slack Calculation, Input to Flip-flop Path Flip-flop to Output Path 256 Flip-flop to Output Path with Actual Clock, Input to Output Path Multicycle Paths 260 Crossing Clock Domains, False Paths Half-Cycle Paths Removal Timing Check Recovery Timing Check Timing across Clock Domains Slow to Fast Clock Domains Fast to Slow Clock Domains Examples 295 Half-cycle Path - Case 1, 296 Half-cycle Path - Case 2, 298 Fast to Slow Clock Domain, 301 Slow to Fast Clock Domain, 303 x

8 8.10 Multiple Clocks Integer Multiples Non-Integer Multiples Phase Shifted 314 CHAPTER 9: Interface Analysis IO Interfaces Input Interface 318 Waveform Specification at Inputs, 318 Path Delay Specification to Inputs, Output Interface 323 Output Waveform Specification, 323 External Path Delays for Output, Output Change within Window SRAM Interface DDR SDRAM Interface Read Cycle Write Cycle 348 Case 1: Internal 2x Clock, 349 Case 2: Internal lx Clock, Interface to a Video DAC 360 CHAPTER 10: Robust Verification On-Chip Variations 365 Analysis with OCV at Worst PVT Condition, 371 OCV for Hold Checks, Time Borrowing 377 Example with No Time Borrowed, 379 Example with Time Borrowed, 382 Example with Timing Violation, Data to Data Checks Non-Sequential Checks Clock Gating Checks 394 Active-High Clock Gating, 396 Active-Low Clock Gating, 403 Clock Gating with a Multiplexer, 406 xi

9 Clock Gating with Clock Inversion, Power Management Clock Gating Power Gating Multi Vt Cells 416 High Performance Block with High Activity, 416 High Performance Block with Low Activity, Well Bias Backannotation SPEF SDF Sign-off Methodology 418 Parasitic Interconnect Corners, 419 Operating Modes, 420 PVT Corners, 420 Multi-Mode Multi-Corner Analysis, Statistical Static Timing Analysis Process and Interconnect Variations 423 Global Process Variations, 423 Local Process Variations, 424 Interconnect Variations, Statistical Analysis 427 What is SSTA?, 427 Statistical Timing Libraries, 429 Statistical Interconnect Variations, 430 SSTA Results, Paths Failing Timing? 433 No Path Found, 434 Clock Crossing Domain, 434 Inverted Generated Clocks, 435 Missing Virtual Clock Latency, 439 Large I/O Delays, 440 Incorrect I/O Buffer Delay, 441 Incorrect Latency Numbers, 442 Half-cycle Path, 442 Large Delays and Transition Times, 443 Missing Multicycle Hold, 443 Path Not Optimized, 443 Xll

10 Path Still Not Meeting Timing, 443 What if Timing Still Cannot be Met, Validating Timing Constraints 444 Checking Path Exceptions, 444 Checking Clock Domain Crossing, 445 Validating IO and Clock Constraints, 446 APPENDIX A: SDC 447 A. 1 Basic Commands 448 A.2 Object Access Commands 449 A.3 Timing Constraints 453 A.4 Environment Commands 461 A.5 Multi-Voltage Commands 466 APPENDIX B: Standard Delay Format (SDF) 467 B.l What is it? 468 B.2 The Format 471 Delays, 480 Timing Checks, 482 Labels, 485 Timing Environment, 485 B.2.1 Examples 485 Full-adder, 485 Decade Counter, 490 B.3 The Annotation Process 495 B.3.1 Verilog HDL 496 B.3.2 VHDL 499 B.4 Mapping Examples 501 Propagation Delay, 502 Input Setup Time, 507 Input Hold Time, 509 Input Setup and Hold Time, 510 Input Recovery Time, 511 Input Removal Time, 512 Period, 513 Pulse Width, 514 Input Skew Time, 515

11 No-change Setup Time, 516 No-change Hold Time, 516 Port Delay, 517 Net Delay, 518 Interconnect Path Delay, 518 Device Delay, 519 B.5 Complete Syntax 519 APPENDIX С: Standard Parasitic Extraction Format (SPEF). 531 C.l Basics 531 C.2 Format 534 C.3 Complete Syntax 550 Bibliography 561 Index 563 XIV