Quiz #4 Thursday, April 25, 2002, 5:30-6:45 PM

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1 Last (family) name: First (given) name: Student I.D. #: Circle section: Hu Saluja Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE/CS 352 Digital System Fundamentals Quiz #4 Thursday April :3-6:45 PM Instructions:. Closed book examination. 2. No calculator hand-held computer or portable computer allowed. 3. Five points penalty if you fail to enter name ID# or instructor selection. 4. Answer must be entered into specified boxes if provided. 5. You must show your work to receive full or partial credit for your answers. 6. No one shall leave room during last 5 minutes of the examination. 7. Upon announcement of the end of the exam stop writing on the exam paper immediately. Pass the exam to isles to be picked up by a TA. The instructor will announce when to leave the room. 8. Failure to follow instructions may result in forfeiture of your exam and will be handled according to UWS 4 Academic misconduct procedures. ECE/CS 352 Quiz #3 /9/2

2 Problem Points Score Total. (5 points) Registers (a) (5 points) The content of a 4-bit bi-directional shift register with parallel load (shown in the text book as SHR4) was initially. The parallel load data is. The right serial input (RSI) is connected to a logic and the left serial input (LSI) is connected to the left serial output Q 3 as shown below: Q 3 Q 2 Q Q RSI S S SHR 4 LSI D 3 D 2 D D Specify the output of this shift register Q 3 Q 2 Q Q after executing the operation on the left in each row of the following table. Operations Q 3 Q 2 Q Q Initially Left shift left shift Parallel load Right shift Left shift S2 ECE/CS 352 Quiz #4 2

3 (b) ( points) A 4-bit multi-function register operates according to a function table where S S are two mode selection inputs. S S Register operation No change Load Parallel data 's Complement of current content Shift left This register is to be implemented by cascading four identical -bit modules. The i -th bit module has two outputs Qi ( t ) and Qi () t and four external inputs S S I i (t) (parallel load data) and Q i (t) (shift left). Implement this i -th bit module using a D-type positive edge triggered flip-flop and a SOP realization of flip-flop input equations with minimum number of AND OR NOT logic gates. Give the logic diagram D Q i (t) Q i (t) clock ECE/CS 352 Quiz #4 3

4 2. (25 points) Counters (a) (3 points) A 4-bit ring counter is implemented with a (right-shift) shift register that will be initialized to a value of. Specify the remaining counter outputs of this ring counter in correct order. (b) (4 points) A switch-tail ring counter (a.k.a. Johnson counter twist ring counter) uses the complement of the serial output as the serial input to a (right-shift) shift register. If such a counter is initialized with specify the remaining counter outputs. ECE/CS 352 Quiz #4 4

5 (c) (8 points) CTR4 is the four bit up-counter with parallel load discussed in the text book. CO is carry out and is not needed for this problem. Our goal is to design a counter that will count from the excess-3 coded decimal digits:. Use as few as possible logic gates and a single CTR4 counter to design this synchronous excess-3 binary coded counter. Use "" to indicate logic and "" to indicate logic where-ever needed in your implementation. Specify the K-map of the input Load. Clock CTR4 Load Count D Q D Q D 2 Q 2 D 3 Q 3 CO Q 3 Q 2 \Q Q ECE/CS 352 Quiz #4 5

6 (d) ( points) Draw the logic diagram of a 3-bit synchronous binary down-counter that counts in the following sequence:. Use 3 J-K type flip-flops and AND OR NOT logic gates. Specify count enable signal EN and carry out signal CO. The JK flip-flop excitation table is provided for your convenience. Q J Q K Q J Q Q K Q J Q Q 2 K Q Clock JK Flip-Flop Q(t) Q(t+) J K X X X X ECE/CS 352 Quiz #4 6

7 3. (2 points) Memory organization (CHAPTER 6 WILL NOT BE ON QUIZ 4) (a) (4 points) With coincident selection scheme (2D memory) a 28K memory employs two decoders to provide the row select and column select signals. Suppose there are twice as many row-select lines (they are output lines of the row select decoder) than the column-select lines. How many address lines are feeding into the column-select decoder? address lines are connected to the column select decoder. (b) (4 points) A 64K memory chip is made of a square memory cell arrays. First part (most significant bits) of an address will feed into the row-select decoder and the remaining address lines will feed into column select decoder. Suppose the address in hexdecimal format is A2BE H. Find the physical location (column and row numbers) of the memory cell that is addressed. Row number: = ; column number: =. (c) (3 points) How many 6K 4 RAM chips are required to build a 28K 6 RAM subsystem? chips. ECE/CS 352 Quiz #4 7

8 (d) (4 points) A random access read/write memory is constructed of four 24 word by 4 bit integrated circuits chips with all address data and R/W lines tied in parallel (ie: A on Chip to A on Chip to A on Chip 2 to A on Chip 3 etc.). The chip select lines are separately tied to the outputs of a 2-line to -of-4 decoder which has S and S inputs tied to Address bit A and A respectively. Fill in the blanks below RAM 24 4 RAM 24 4 RAM 24 4 RAM DATA DATA DATA DATA ADRS CS ADRS CS ADRS CS ADRS CS R/W R/W R/W R/W R/W A(9:) A(:) 2 2-to-4 Decoder The size of the RAM is (e) (5 points) Connect the inputs of three 3-state buffers so that it implements a Boolean function G = A B + C D + E F where A+C+E = and A C=C E=E A = ECE/CS 352 Quiz #4 8

9 4. (25 points) PLA PAL implementation (CHAPTER 6 WILL NOT BE ON QUIZ 4) (a) (8 points) Implement the following two Boolean functions using a PLA. The objective is to minimize the number of product terms needed. Give your answer by filling in the PLA programming table below. You should also specify that whether the outputs need to be Complemented (C) or remain in original form: True (T). Note that you should not need more than six product terms! F ( a b c) = F ( a b c) = 2 m(57) m(46) Product Inputs Outputs Term a b c F F 2 Enter T or C: ECE/CS 352 Quiz #4 9

10 (b) (9 points) The following four Boolean functions are to be implemented using a PAL that has 3 inputs four outputs and a two-wide AND-OR structure (each output OR gate has two inputs). Complete the PAL connection map below. Label each output or the OR gates and mark each required connection with. = = = = (2347) ) ( (234) ) ( (456) ) ( (367) ) ( m z y x D m z y x C m z y x B m z y x A x y z w z y x ECE/CS 352 Quiz #4 z

11 (c) (8 points) For the same set of Boolean functions as specified in part (b) implement them using a ROM. Specify the minimum size of the ROM and its address and corresponding contents: The minimum size of the ROM is by. The addresses and contents are: Address Content ECE/CS 352 Quiz #4

12 5. (5 points) Hazards The circuit shown below is constructed of gates that have a delay of 5 nanoseconds. Initially all signals are stable as shown on the left edge of the diagram. Inputs "D" and "S" simultaneously change from to while D remains stable at "" causing the change shown in signal "a" and no change in signal "d". D S a d b F D c 5 ns. D D S a b c d F (a) (6 points) On the diagram above plot the waveforms for "b" "c" and "F". ECE/CS 352 Quiz #4 2

13 (b) (3 points) Circle the type of hazard that the circuit will have. (CIRCLE ALL THAT ARE TRUE) SICS SICS Function Dynamic Zero One Hazard Hazard Hazard Hazard (MICS Hazard) (c) (6 points) A Boolean function f(a B C D) is implemented in SOP format as follows: f ( ABCD ) = AD + BC D+ ABC Identify ALL the product terms that need to be added to this SOP expression to guarantee that it is free of all the static and dynamic hazards. ECE/CS 352 Quiz #4 3

Final Exam review: chapter 4 and 5. Supplement 3 and 4

Final Exam review: chapter 4 and 5. Supplement 3 and 4 1. A new type of synchronous flip-flop has the following characteristic table. Find the corresponding excitation table with don t cares used as much