A.R. ENGINEERING COLLEGE, VILLUPURAM ECE DEPARTMENT

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1 .R. ENGINEERING COLLEGE, VILLUPURM ECE EPRTMENT QUESTION BNK SUB. NME: IGITL ELECTRONICS SUB. COE: EC223 SEM: III BRNCH/YER: ECE/II UNIT-I MINIMIZTION TECHNIQUESN LOGIC GTES PRT- ) efine Minterm & Maxterm. 2) What are the methods adopted to reduce Boolean function? 3) What is a karnaugh map? 4) State the limitations of karnaugh map? 5) Explain list out the advantages and disadvantages of K-map method? 6) List out the advantages and disadvantages of Quine-Mc Cluskeymethod? 7) efine uality Theorem? 8) State e Morgan's theorem. 9) What are called don t care conditions? ) What is a Logic gate? ) Which gates are called as the universal gates? What are its advantages? 2) What are the types of TTL logic? 3) List the different versions of TTL 4) State advantages and disadvantages of TTL 5) efine duality property. 6) What is a Logic gate? 7) efine the sum of products? 8) efine the product of sum? 9) What are the methods adopted to reduce Boolean function? PRT-B ) i) Prove that (x+x2).(x. x3 +x3) (x2 + x.x3) =x x2 (8) ii) Simplify using K-map to obtain a minimum POS expression: ( + B +C+) (+B +C+) (+B+C+ ) (+B+C + ) ( +B+C + ) (+B+C +) (8) 2) Reduce the following equation using Quine McClucky method of minimization F (,B,C,) = m(,,3,4,5,7,,3,4,5) (6) 3) i) State and Prove idempotent laws of Boolean algebra. (8) ii) Using a K-Map, Find the MSP from of F= (, 4, 8, 2, 3, 7,, 5) +_d (5) (8) 4) Using a K-Map, Find the MSP form of F= (-3, 2-5) + _d (7, ) (6).R ENGINEERING COLLEGE,VILLUPURM Page

2 5) i) Simplify the following using the Quine McClusky minimization technique (8) = f(a,b,c,d) = (,,2,3,6,7,8,9,4,5).oes Quine McClusky take care of don t care conditions? In the above problem, will you consider any don t care conditions? Justify your answer ii) List also the prime implicants and essential prime implicants for the above case (8) 6) i) etermine the MSP and MPS focus of F= (,2,6,8,,2,4,5) (8) ii) State and Prove emorgan s theorem (8) 7) etermine the MSP form of the Switching function F = (,,4,5,6,,4,5,6,7,2-22,3,32,33,36,37,48,49,52,53,56,63) (6) 8) i) etermine the MSP form of the Switching function (8) F( a,b,c,d) = (,2,4,6,8) + d(,,2,3,4,5) ii) Find the Minterm expansion of f(a,b,c,d) =a (b +d)+acd (8) 9) Simplify the following Boolean function by using the Tabulation Method F= (,, 2, 8,,, 4, 5) (6) ) Find a Min SOP and Min POS for f = b c d + bcd + acd + a b c + a bc d (6) ) Find an expression for the following function using Quine McCluscky method F= (, 2, 3,5,7,9,,3,4,6,8,24,26,28,3) (6) 2) State and prove the theorems of Boolean algebra with illustration 3) Find the MSP representation for F(,B,C,,E) = m(,4,6,,2,22,24,26) + d (,,6,27) using K-Map method, raw the circuit of the minimal expression using only NN gates (6) 4) i) Show that if all the gates in a two level N-OR gate networks are replaced by (8) NN gates the output function does not change ii) Why does a good logic designer minimize the use of NOT gates? (8) 5) Simplify the Boolean function F(,B,C,) = m (,3,7,,5) + d (,2,5).if don t care conditions are not taken care, What is the simplified Boolean function.what are your comments on it? Implement both circuits (6) 6) i) Show that if all the gate in a two level OR-N gate network are replaced by NOR gate, the output function does not change. (8) ii) Implement Y = (+C) (+ ) ( +B+C ) using NOR gates only (8) 7 ) i) Show that the NN operation is not distributive over the N operation (8) ii) Find a network of N and OR gate to realize f(a,b,c,d) = m (,5,6,,3,4) (8) 8) i) What is the advantages of using tabulation method? (8) ii) etermine the prime implicants of the following function using tabulation method F( W,X,Y,Z) = (,4,6,7,8,9,,,5) (8 ) 9) i) Given the following Boolean function F= C + B + B C + BC ii) Express it in sum of minterms & Find the minimal SOP expression (8) 2) Explain the operation of 3 I/P TTL NN Gate with required diagram and truth table. (6) 2) Explain the operation of CMOS NN and NOR Gate with the circuits and truth Table (6).R ENGINEERING COLLEGE,VILLUPURM Page 2

3 UNIT-II COMBINTIONL CIRCUITS PRT- ) efine combinational logic 2) Explain the design procedure for combinational circuits 3) efine half adder and full adder 4) efine ecoder? 5) What is binary decoder? 6) efine Encoder? 7) What is priority Encoder? 8) efine multiplexer? 9) What do you mean by comparator? ) What is BC adder? ) What is Magnitude Comparator? 2) What is code converter? 3) Give the applications of emultiplexer. 4) Mention the uses of emultiplexer 5) Give other name for Multiplexer and emultiplexer. 6) List out the applications of multiplexer? 7) efine half subtractor and full subtractor. 8) What is meant by parity generation and checking? 9) 4bit binary adder parallel binary adder? PRT-B ) Implement the switching function F= (,,3,4,7) using a 4 input MUX and explain (6) 2) Explain how will build a 64 input MUX using nine 8 input MUXs (6) 3) Implement the switching function F= (,,3,4,2,4,5) using an 8 input MUX (6) 4) Explain how will build a 6 input MUX using only 4 input MUXs (6) 5) Explain the operation of 4 to line decoder with necessary logic diagram (6) 6) i) esign full adder and full sub tractor. (8) ii ) esign a 4 bit magnitude comparator to compare two 4 bit number (8) 7) Construct a combinational circuit to convert given binary coded decimal number into an Excess 3 code for example when the input to the gate is then the circuit should generate output as (6) 8) i) Using a single 7483, draw the logic diagram of a 4 bit adder/sub tractor (8) ii) Realize a Binary to BC conversion circuit starting from its truth table (8) 9) esign a combinational circuit which accepts 3 bit binary number and converts its equivalent excess 3 code (6) ) i) Explain carry look ahead adder. (8) ii) raw and explain BC adder. (8).R ENGINEERING COLLEGE,VILLUPURM Page 3

4 UNIT-III ) efine Flip flop. 2) What are the different types of flip-flop? 3) What is the operation of RS flip-flop? 4) What is the operation of SR flip-flop? 5) What is the operation of flip-flop? 6) What is the operation of JK flip-flop? 7) What is a master-slave flip-flop? 8) efine race around condition. 9) What is edge-triggered flip-flop? ) efine registers. SEQUENTIL CIRCUITS PRT- ) efine shift registers. 2) Write the uses of a shift register 3) What are the different types of shift type? 4) What is the difference between synchronous and asynchronous counter? 5) Name the different types of counter. 6) What is up counter? 7) What is down counter? 8) What is up/down counter? 9) What is a ripple counter? 2) What are the uses of a counter? 2) efine state diagram 22) What is the use of state diagram? 23) What is state table? 24) What is a state equation? 25) What is the classification of sequential circuits? 26) efine sequential circuit? PRT-B ) Explain the operation of JK and clocked JK flip-flops with suitable diagrams (6) 2) raw the state diagram of a JK flip- flop and flip flop (6) 3) esign and explain the working of a synchronous mod 3 counter (6) 4) esign and explain the working of a synchronous mod 7 counter (6) 5) i) esign a synchronous counter with states,, 2,3,,. Using JK FF (8) ii) Using SR flip flops, design a parallel counter which counts in the sequence (8),,,,,,. 6) i) Using JK flip flops, design a parallel counter which counts in the sequence (8),,,,,,. ii) raw and explain Master-Slave JK flip-flop (8) 7) raw as asynchronous 4 bit up-down counter and explain its working (6) 8) Using flip flop,design a synchronous counter which counts in the sequence (6).R ENGINEERING COLLEGE,VILLUPURM Page 4

5 ,,,,,,,, 9) esign a binary counter using T flip flops to count in the following sequences i),,,,,,,, ii),,,,, (6) ) i) esign a 3 bit binary Up-own counter ii) raw and explain the operation of four bit Johnson counter (8) ) nalyze the given shown in fig. obtains the state table and state diagram and determine the function of the circuit (6) X X2 Z J CLK Z2 K 2) Minimize the following state table. (6) PRESENT NEXT STTE OUTPUT (z) STTE X= X= X= X= B C E F G h C B C.R ENGINEERING COLLEGE,VILLUPURM Page 5

6 UNIT-IV MEMORY EVICES PRT- ) Classification of memories? 2) List basic types of programmable logic devies 3) efine ROM 4) Explain ROM 5) What are the types of ROM? 6) efine ROM. 7) List the basic types of RMs 8) Explain PROM. 9) Explain EPROM ) Explain EEPROM. ) What is RM? 2) efine RM 3) List the two categories of RMs. 4) Why RMs are called as Volatile? 5) efine Static RM and dynamic RM 6) List the two types of SRM 7) List the basic types of RMs 8) efine address and word: 9) What are the types of ROM. 2) What is programmable logic array? How it differs from ROM? 2) Why was PL developed? 22) Why the input variables to a PL are buffered 23) List the major differences between PL and PL 24) efine PL. 25) Give the classification of PLs. 26) efine FPG. 27) Comparison between SRM & RM 28) Comparison between PROM, PL, PL PRT-B ) i) raw a RM cell and explain its working. (8) ii )Write short notes on (i) RM (ii) Types of ROM s (8) 2) List the PL program table for BC to Excess -3-code convertor circuits and show its implementation for any two output functions (6) 3) Generate the following Boolean functions with PL with 4inputs and 4outputs Y3= BC + BC + BC+B Y2= BC + BC+BC Y= BC + BC+B C+BC Y=BC (6).R ENGINEERING COLLEGE,VILLUPURM Page 6

7 4) implement the following functions using PL. (6) F= m(,2,4,6); F2= m(,,6,7) F3= m(2,6) 5) Implement the given functions using PROM and PL (6) F= m(,,3,5,7,9); F2= m(,2,4,7,8,,)) Implement the given functions using PL F= m(,,2,4,6,7); F2= m(,3,5,7); F3= m(,2,3,6) (6) 6) i) raw the block diagram of a PL device and briefly explain each block. (8) ii ) Write short note on Field Programmable Gate rray (FPG) (8) 7) i) esign a 6 bit ROM array and explain the operation (8) ii ) Write short note on Field Programmable Gate rray (FPG) (8) UNIT-5 SYNCHRONOUS N YNCHRONOUS SEQUENTIL CIRCUITS PRT- ) What is the classification of sequential circuits? 2) Give the comparison between synchronous & synchronous sequential circuits? 3) efine synchronous sequential circuit? 4) Give the comparison between synchronous & synchronous counters? 5) What are the steps for the design of asynchronous sequential circuit? 6) What are the steps for the design of asynchronous sequential circuit? 7) What are the types of asynchronous circuits? 8) What is fundamental mode? 9) What is fundamental mode sequential circuit? ) What is pulse mode circuit? ) What are the problems involved in asynchronous circuits? 2) efine hazards. 3) What are the types of shift register? 4) State the types of counter? 5) What are the 6basic building blocks of algorithmic state machine chart? 6) What is combinational circuit? PRT-B ) What is the objective of state assignment in asynchronous circuit? (6) 2) Realization for the following Boolean function f(,b,c,) = m(,2,6,7,8,,2) (6) 3) Summarize the design procedure for asynchronous sequential circuit iscuss on Hazards and races (6) 4) evelop the state diagram and primitive flow table for a logic system that has 2 inputs, x nd y and an output z.nd reduce primitive flow table. The behavior of the circuit is stated as follows. Initially x=y=. Whenever x= and y = then z=, whenever x = and y = then z =.When x=y= or x=y= no change.r ENGINEERING COLLEGE,VILLUPURM Page 7

8 in z to remains in the previous state. The logic system has edge triggered inputs with out having a clock.the logic system changes state on the rising edges of the 2 inputs. Static input values are not to have any effect in changing the Z output. (6) 5) pulse mode asynchronous machine has two inputs. It produces an output whenever two consecutive pulses occur on one input line only. The output remains at until a pulse has occurred on the other input line. raw the state table for the machine (6) 6) Construct the state diagram and primitive flow table for an asynchronous network that has two inputs and one output. The input sequence XX2 =,, causes the output to has two inputs and one output. (6) 7) iscuss on the different types of Hazards that occurs in asynchronous sequential circuits. (6) 8) Write short note on races and cycles that occur in fundamental mode circuits. (6) 9) esign an asynchronous sequential circuit with two inputs X and Y and with one output Z. Whenever Y is,(6) input X is transferred to Z. When Y is,the output does not change for any change in X. (6).R ENGINEERING COLLEGE,VILLUPURM Page 8

Department of Computer Science and Engineering Question Bank- Even Semester:

Department of Computer Science and Engineering Question Bank- Even Semester: 2014-2015 CS6201& DIGITAL PRINCIPLES AND SYSTEM DESIGN (Common to IT & CSE, Regulation 2013) UNIT-I 1. Convert the following