CS/ECE 250: Computer Architecture. Basics of Logic Design: ALU, Storage, Tristate. Benjamin Lee

Transcription

1 CS/ECE 25: Computer Architecture Basics of Logic esign: ALU, Storage, Tristate Benjamin Lee Slides based on those from Alvin Lebeck, aniel, Andrew Hilton, Amir Roth, Gershon Kedem

2 Homework #3 ue Mar 7, :55pm Administrivia Readings Pragmatic Logic by William Eccles Linked on web page, skim for what you need. Combinational Circuits Ch , Ch 5.3 Sequential Circuits Ch 6 CS/ECE 25 2

3 Arithmetic and Logical Operations in ISA What operations are there? How do we implement them? Consider a -bit Adder CS/ECE 25 3

4 A -bit Full Adder Cin a b Sum + Cout a b C in Sum C out CS/ECE 25 4

5 Example: 4-bit Ripple Carry Adder S3 S2 S S C out Full Adder Full Adder Full Adder Full Adder b3 a3 b2 a2 b a b a CS/ECE 25 5

6 Subtraction How do we perform integer subtraction? What is the HW? Remember: Subtraction is just addition X Y = X + (-Y) = X + (~Y +) CS/ECE 25 6

7 Example: Adder/Subtractor S3 S2 S S C out Full Adder Full Adder Full Adder Full Adder Add/Sub b3 a3 b2 a2 b a b a CS/ECE 25 7

8 Overflow How would we detect signed overflow? See if CI!= CO -bit!= is implemented with XOR If CI = and CO= Sum must produce the carry CO= only if A= and B= Adding two negative numbers to produce positive number If CI = and CO= Sum must consume the carry CO= only if A= and B= Adding two positive numbers to produce a negative number CS/ECE 25 8

9 Add/Subtract With Overflow etection Overflow S n- S n- 2 S S Full Adder Full Adder Full Adder Full Adder Add/Sub b n- a n- b n- 2 a n- 2 b a b a CS/ECE 25 9

10 ALU Slice C in a b 3 2 A F a + b a - b - NOT b - 2 a OR b - 3 a AN b Add/sub 2 Add/sub C ou t F CS/ECE 25

11 The ALU Overflow = Zero n- n-2 ALU Slice ALU Slice ALU Slice ALU Slice ALU control b n- a n- b n-2 a n-2 b a b a CS/ECE 25

12 Abstraction: The ALU General structure Two operand inputs Control inputs ALU Operation We can build circuits for Multiplication ivision They are more complex Input A Input B ALU Carry Out Zero Result Overflow CS/ECE 25 2

13 Shifts Remember the << and >> operations? Shift left/shift right? How would we implement these? Suppose an 8-bit number b 7 b 6 b 5 b 4 b 3 b 2 b b Shifted left by a 3 bit number s 2 s s Option : Truth Table? 248 rows? Not appealing CS/ECE 25 3

14 Let s simplify Simpler problem: 8-bit number shifted by bit number (shift amount selects each mux) b 7 out 7 b 6 out 6 b 5 b 4 out 5 out 4 b 3 out 3 b 2 out 2 b out b CS/ECE 25 out 4

15 Let s simplify Simpler problem: 8-bit number shifted by 2 bit number (new muxes selected by 2 nd bit) b 7 out 7 b 6 out 6 b 5 b 4 out 5 b 3 b 2 out 4 out 3 b out 2 b out out CS/ECE 25 5

16 Now shifted by 3-bit number Full problem: 8-bit number shifted by 3 bit number (new muxes selected by 3 rd bit) b 7 b 6 out 7 out 6 b 5 b 4 b 3 b 2 out 5 out 4 out 3 b out 2 b out out CS/ECE 25 6

17 Now shifted by 3-bit number Shifter in action: shift by b 7 b 6 out 7 out 6 b 5 b 4 b 3 b 2 out 5 out 4 out 3 b out 2 b out out CS/ECE 25 7

18 Now shifted by 3-bit number Shifter in action: shift by b 7 b 6 out 7 out 6 b 5 b 4 b 3 b 2 out 5 out 4 out 3 b out 2 b out out CS/ECE 25 8

19 Now shifted by 3-bit number Shifter in action: shift by b 7 b 6 out 7 out 6 b 5 b 4 b 3 b 2 out 5 out 4 out 3 b out 2 b out out CS/ECE 25 9

20 So far We can make logic to compute math Add, subtract, (we ll see multiply/divide later) Bitwise: AN, OR, NOT, Shifts Selection (MUX) But processors need state (hold value) Registers CS/ECE 25 2

21 Memory Elements All the circuits we looked at so far are combinational circuits: the output is a Boolean function of the inputs. We need circuits that can remember values (registers, memory) The output of the circuit is a function of the input and a stored value (state) Circuits with memory are called sequential circuits Key to storage: loops in circuit from outputs to inputs CS/ECE 25 2

22 NOR-based Set-Reset (SR) Latch R R S S R S - on t set both S & R to. Seriously, don t do it. CS/ECE 25 22

23 Set-Reset Latch (Continued) R R S S Time S R CS/ECE 25 23

24 Set-Reset Latch (Continued) R R S S Time S Set Signal Goes High R Output Signal Goes High CS/ECE 25 24

25 Set-Reset Latch (Continued) R R S S Time S Set Signal Goes Low R Output Signal Stays High CS/ECE 25 25

26 Set-Reset Latch (Continued) R R S S Time S Until Reset Signal Goes High R Then Output Signal Goes Low CS/ECE 25 26

27 SR Latch ownside: S and R at once = chaos ownside: Bad interface What is a better solution? CS/ECE 25 27

28 ata Latch ( Latch) Starting with SR Latch CS/ECE 25 28

29 ata Latch ( Latch) E nable ata Starting with SR Latch Change interface to ata + Enable ( + E) CS/ECE 25 29

30 ata Latch ( Latch) E nable ata Time E - E goes high E latched Stays as output CS/ECE 25 3

31 ata Latch ( Latch) E nable ata E - E goes low E Time oes not affect Output Output unchanged By changes to CS/ECE 25 3

32 ata Latch ( Latch) E nable ata Time E - E goes high E latched Becomes new output CS/ECE 25 32

33 ata Latch ( Latch) E nable ata Time E - Slight elay (Logic gates take time) E CS/ECE 25 33

34 Logic takes time: Logic Takes Time Gate delays: delay to switch each gate Wire delays: delay for signal to travel down wire Other factors (not going into them here) Need to make sure that signals timing is right on t want to have races CS/ECE 25 34

35 Clocks Processors have a clock: Alternates (low high low high) Latch à logic à latch in one clock cycle One clock cycle 3.4 GHz processor = 3.4 Billion clock cycles/sec CS/ECE 25 35

36 Level Triggered Clock First thoughts: Level Triggered Latch enabled when clock is high Hold value when clock is low 3 Logic latch 3 E latch E Clk CS/ECE 25 36

37 Level Triggered Clock How we d like this to work Clock is low, all values stable Clk 3 Logic latch 3 E latch E Clk CS/ECE 25 37

38 Level Triggered Clock How we d like this to work Clock goes high, latches capture and transmit new value Clk 3 Logic latch 3 E latch E Clk CS/ECE 25 38

39 Level Triggered Clock How we d like this to work Signals work their way through logic w/ high clk Clk 3 Logic latch 3 E latch E Clk CS/ECE 25 39

40 Level Triggered Clock How we d like this to work Clock goes low before signals reach next latch Clk 3 Logic latch 3 E latch E Clk CS/ECE 25 4

41 Level Triggered Clock How we d like this to work Clock goes low before signals reach next latch Clk 3 Logic latch 3 E latch E Clk CS/ECE 25 4

42 Level Triggered Clock How we d like this to work Everything stable before clk goes high Clk 3 Logic latch 3 E latch E Clk CS/ECE 25 42

43 Level Triggered Clock How we d like this to work Clk goes high again, repeat Clk 3 Logic latch 3 E latch E Clk CS/ECE 25 43

44 Level Triggered Clock Problem: What if signal reaches latch too early? i.e., while clk is still high Clk 3 Logic latch 3 E latch E Clk CS/ECE 25 44

45 Level Triggered Clock Problem: What if signal reaches latch too early? Signal goes right through latch, into next stage.. Clk 3 Logic latch 3 E latch E Clk CS/ECE 25 45

46 That would be bad Getting into a stage too early is bad Something else is going on there à corrupted Also may be a loop with one latch Consider incrementing counter (or PC) Too fast -- increment twice? Not good. latch E + 3 CS/ECE 25 46

47 Edge Triggered Instead of level triggered Latch a new value at a clock level (high or low) We use edge triggered Latch a value at an clock edge (rising or falling) Rising Edges Falling Edges CS/ECE 25 47

48 Flip-Flop C latch E latch E Rising edge triggered Flip-flop Two Latches w/ Opposite clking of enables CS/ECE 25 48

49 Flip-Flop C latch E latch E Rising edge triggered Flip-flop Two Latches w/ opposite clking of enables On Low Clk, first latch enabled (propagates value) Second not enabled, maintains value CS/ECE 25 49

50 Flip-Flop C latch E latch E Rising edge triggered Flip-flop Two Latches w/ opposite clking of enables On Low Clk, first latch enabled (propagates value) Second not enabled, maintains value On High Clk, second latch enabled First latch not enabled, maintains value CS/ECE 25 5

51 Flip-Flop latch E latch E latch E latch E C C No possibility of races Even if I put 2 FFs back-to-back By the time signal gets through 2 nd latch of st FF, st latch of 2 nd FF is disabled Still must ensure signals reach FF before clk rises Important concern in logic design is making timing CS/ECE 25 5

52 Flip-flops (continued ) Could also do falling edge triggered Switch which latch has NOT on clk Flip-flop is ubiquitous Typically people just say latch and mean FF Which edge is used does not matter As long as same edge is used consistently We will use rising edge CS/ECE 25 52

53 flip flops Generally do not draw clk input Have one global clk, assume it goes there Often see > as symbol meaning clk Maybe have explicit enable Might not want to write every cycle If no enable signal shown, implies always enabled FF > FF FF E Get output and NOT(output) for free CS/ECE 25 53

54 Register File Can store one value what about manyvalues? E.g., Register File (the physical storage for the regs) MIPS, bit integer registers How do we build a Register File using Flip-Flops? What other components do we need? CS/ECE 25 54

55 Register File Reading the registers 32 input mux -- slow Need MUXes -- big Other regs not pictured 32 bit reg E 32 bit reg E 32 bit reg E 32 bit reg E CS/ECE 25 55

56 Register File Reading the registers 32 input mux -- slow Need MUXes -- big Other regs not pictured Writing the registers Need to pick which reg Have reg num (e.g., 9) Make En9= En, En, = Wrata En En En3 En3 32 bit reg E 32 bit reg E 32 bit reg E 32 bit reg E CS/ECE 25 56

57 ecoders First task: convert binary number to one hot N bits in 2 N bits out 2 N - bits are, bit (matching the input) is 3 ecoder CS/ECE 25 57

58 ecoder Logic ecoder basically AN gates for each output: Out only True (one) if input In Out In In 2 3-input gates are fine. In theory, gates can have any # of inputs In practice >4 converted to multiple gates CS/ECE 25 58

59 ecoder Logic ecoder basically AN gates for each output: Out only True (one) if input Out In Out In In 2 Repeat for all outputs AN together correct sets of bits CS/ECE 25 59

60 Register File ecoder supports register addressing: Use decoder to convert register number into control signal Send write data to all registers Use one hot encoding to enable destination register Need to fix register read speed 32 input mux is not realistic For tractability, expand our world from {,} to {,, Z} CS/ECE 25 6

61 Water Analogy To understand Z, let s make an analogy Think of a wire as a pipe Has water = Has water = This wire is (it has no water) CS/ECE 25 6

62 Water Analogy To understand Z, let s make an analogy Think of a wire as a pipe Has water = Has water = This wire is (its full of water) CS/ECE 25 62

63 Water Analogy To understand Z, let s make an analogy Think of a wire as a pipe Has water = Has water = Suppose a gate drives a onto this wire rain the water CS/ECE 25 63

64 Water Analogy To understand Z, let s make an analogy Think of a wire as a pipe Has water = Has water = Suppose a gate drives a onto this wire rain the water CS/ECE 25 64

65 Water Analogy To understand Z, let s make an analogy Think of a wire as a pipe Has water = Has water = Suppose a gate drives a onto this wire rain the water CS/ECE 25 65

66 Water Analogy To understand Z, let s make an analogy Think of a wire as a pipe Has water = Has water = Suppose a gate drives a onto this wire rain the water CS/ECE 25 66

67 Water Analogy To understand Z, let s make an analogy Think of a wire as a pipe Has water = Has water = Suppose the gate now drives a Pump the water CS/ECE 25 67

68 Water Analogy To understand Z, let s make an analogy Think of a wire as a pipe Has water = Has water = Suppose the gate now drives a Pump the water CS/ECE 25 68

69 Water Analogy To understand Z, let s make an analogy Think of a wire as a pipe Has water = Has water = Suppose the gate now drives a Pump the water CS/ECE 25 69

70 Remember this rule? o not connect two outputs to the same wire a b c d BA! One gate drives. The other drives. One pumps water in. The other drains water out Except it s not water, it s electric charge Short circuit à lots of current à lots of heat CS/ECE 25 7

71 A third option: Z There is a third possibility: Z ( high impedance ) Neither pumping or draining charge Prevents charge from flowing through Gate that gives us Z : Tri-state E E - Z CS/ECE 25 7

72 Tri-State Buffers It s ok to connect multiple outputs together under one circumstance -- all but one must be outputting Z at any time n- n-2 E n- E n-2 E E CS/ECE 25 72

73 Mux with Tri-State Buffers Much more efficient for large #s of inputs (e.g., 32) ecoder ensures only one output 32 bit reg E 32 bit reg E 32 bit reg 5 ecoder CS/ECE 25 E 32 bit reg E 73

74 Ports Read Ports Ability to do one read per clock cycle May want more -- read two source registers per instruction Maybe even more if we do many instrs at once (later ) Could add more: need to replicate port Another decoder Another set of tri-states Another output bus (wire connecting the tri-states) Write Ports Ability to do one write/cycle Could add more: need to multiplex write values CS/ECE 25 74

75 Minor etail This is not how a register file is implemented in today s processors (Though it is how other things are implemented) Actually done with SRAM We ll see that later this semester CS/ECE 25 75