ECE 250 / CPS 250 Computer Architecture. Basics of Logic Design ALU and Storage Elements

Transcription

1 ECE 25 / CPS 25 Computer Architecture Basics of Logic esign ALU and Storage Elements Benjamin Lee Slides based on those from Andrew Hilton (uke), Alvy Lebeck (uke) Benjamin Lee (uke), and Amir Roth (Penn)

2 The ALU Overflow = Zero n- n-2 ALU Slice ALU Slice ALU Slice ALU Slice ALU control a n- b n- a n-2 b n-2 a b a b ECE/CS 25 2

3 Abstraction: The ALU General structure Two operand inputs Control inputs ALU Operation We can build circuits for Multiplication ivision They are more complex Input A Input B ALU Carry Out Zero Result Overflow ECE/CS 25 3

4 Another Operations We Might Want: Shift Remember the << and >> operations? Shift left/shift right? How would we implement these? Suppose you have an 8-bit number b 7 b 6 b 5 b 4 b 3 b 2 b b And you can shift it left by a 3-bit number s 2 s s Option : Truth Table? 2 = 248 rows? Yuck. ECE/CS 25 4

5 Let s simplify Simpler problem: 8-bit number shifted by bit number (shift amount selects each mux) b 7 out 7 b 6 out 6 b 5 b 4 out 5 out 4 b 3 out 3 b 2 out 2 b out b out ECE/CS 25 5

6 Let s simplify Simpler problem: 8-bit number shifted by 2 bit number b 7 out 7 b 6 out 6 b 5 b 4 out 5 b 3 b 2 out 4 out 3 b out 2 b out out ECE/CS 25 6

7 Now shifted by 3-bit number Full problem: 8-bit number shifted by 3 bit number b 7 b 6 out 7 out 6 b 5 b 4 b 3 b 2 out 5 out 4 out 3 b out 2 b out out ECE/CS 25 7

8 Now shifted by 3-bit number Shifter in action: shift by (all muxes have S=) b 7 b 6 out 7 out 6 b 5 b 4 b 3 b 2 out 5 out 4 out 3 b out 2 b out out ECE/CS 25 8

9 Now shifted by 3-bit number Shifter in action: shift by Mux control signals from R to L: S =,, b 7 b 6 out 7 out 6 b 5 b 4 b 3 b 2 out 5 out 4 out 3 b out 2 b out out ECE/CS 25 9

10 Now shifted by 3-bit number Shifter in action: shift by Mux control signals from R to L: S=,, b 7 b 6 out 7 out 6 b 5 b 4 b 3 b 2 out 5 out 4 out 3 b out 2 b out out ECE/CS 25

11 So far We can make logic to compute math Add, subtract and you can do mul/div in 35 Assume for now that mul/div can be built Bitwise: AN, OR, NOT, Shifts (left or right) Selection (MUX) pretty much anything But processors need state (hold value) Registers ECE/CS 25

12 Storage All the circuits we looked at so far are combinational circuits: the output is a Boolean function of the inputs. We need circuits that can remember values (registers, memory) The output of the circuit is a function of the input and a function of a stored value (state) Circuits with storage are called sequential circuits Key to storage: feedback loops from outputs to inputs ECE/CS 25 2

13 Ideal Storage Where We re Headed We want something that can hold bit We want to control when it is re-written bit to be written bit to control when we write flip flop = device that holds one bit ( or ) bit currently being held We re going to dig a bit into the box ECE/CS 25 3

14 FF Step #: Set-Reset (SR) Latch R R S S R S - on t set both S & R to. Seriously, don t do it. ECE/CS 25 4

15 Set-Reset Latch (Continued) R R S S Time S R ECE/CS 25 5

16 Set-Reset Latch (Continued) R R S S Time S Set Signal Goes High R Output Signal Goes High ECE/CS 25 6

17 Set-Reset Latch (Continued) R R S S Time S Set Signal Goes Low R Output Signal Stays High ECE/CS 25 7

18 Set-Reset Latch (Continued) R R S S Time S Until Reset Signal Goes High R Then Output Signal Goes Low ECE/CS 25 8

19 SR Latch ownside: S and R at once = chaos ownside: Bad interface So let s build on it to do better ECE/CS 25 9

20 FF Step #2: ata Latch ( Latch ) R S Starting with SR Latch ECE/CS 25 2

21 ata Latch ( Latch) E nable R ata S Starting with SR Latch Change interface to ata + Enable ( + E) If E=, then R=S=. If E=, then S= and R=! ECE/CS 25 2

22 ata Latch ( Latch) E nable ata R S Time E - E goes high E latched Stays as output ECE/CS 25 22

23 ata Latch ( Latch) E nable ata E goes low E R S Time E - oes not affect Output Output unchanged By changes to ECE/CS 25 23

24 ata Latch ( Latch) E nable ata R S Time E - E goes high E latched Becomes new output ECE/CS 25 24

25 ata Latch ( Latch) E nable ata R S Time E - Slight elay E (Logic gates take time) ECE/CS 25 25

26 Logic Takes Time Logic takes time: Gate delays: delay to switch each gate Wire delays: delay for signal to travel down wire Other factors (not going into them here) Need to make sure that signals timing is right on t want to have races or wacky conditions.. ECE/CS 25 26

27 Processors have a clock: Alternates Clocks Like the processor s internal metronome Latch! logic! latch in one clock cycle One clock cycle 3 GHz processor = 3 Billion clock cycles/sec ECE/CS 25 27

28 FF Step #3: Using Level-Triggered Latches First thoughts: Level Triggered Latch captures new value when clock is high Latch holds existing value when clock is low 3 Logic latch 3 E latch E Clk ECE/CS 25 28

29 Strawman: Level Triggered How we d like this to work Clock is low, all values stable Clk 3 Logic latch 3 E latch E Clk ECE/CS 25 29

30 Strawman: Level Triggered How we d like this to work Clock goes high, latches capture and xmit new val Clk 3 Logic latch 3 E latch E Clk ECE/CS 25 3

31 Strawman: Level Triggered How we d like this to work Signals work their way through logic w/ high clk Clk 3 Logic latch 3 E latch E Clk ECE/CS 25 3

32 Strawman: Level Triggered How we d like this to work Clock goes low before signals reach next latch Clk 3 Logic latch 3 E latch E Clk ECE/CS 25 32

33 Strawman: Level Triggered How we d like this to work Clock goes low before signals reach next latch Clk 3 Logic latch 3 E latch E Clk ECE/CS 25 33

34 Strawman: Level Triggered How we d like this to work Everything stable before clk goes high Clk 3 Logic latch 3 E latch E Clk ECE/CS 25 34

35 Strawman: Level Triggered How we d like this to work Clk goes high again, repeat Clk 3 Logic latch 3 E latch E Clk ECE/CS 25 35

36 Strawman: Level Triggered Problem: What if signal reaches latch too early? I.e., while clk is still high Clk 3 Logic latch 3 E latch E Clk ECE/CS 25 36

37 Strawman: Level Triggered Problem: What if signal reaches latch too early? Signal goes right through latch, into next stage.. Clk 3 Logic latch 3 E latch E Clk ECE/CS 25 37

38 That would be bad Getting into a stage too early is bad Something else is going on there! corrupted Also may be a loop with one latch ECE/CS 25 38

39 FF Step #4: Edge Triggered Instead of level triggered Latch a new value at a clock level (high or low) We use edge triggered Latch a value at an clock edge (rising or falling) Rising Edges Falling Edges ECE/CS 25 39

40 Our Ultimate Goal: Flip-Flop C latch E latch E Rising edge triggered Flip-flop Two Latches w/ opposite clking of enables ECE/CS 25 4

41 Flip-Flop C latch E latch E Rising edge triggered Flip-flop Two Latches w/ opposite clking of enables On Low Clk, first latch enabled (propagates value) Second not enabled, maintains value ECE/CS 25 4

42 Flip-Flop C latch E latch E Rising edge triggered Flip-flop Two Latches w/ opposite clking of enables On Low Clk, first latch enabled (propagates value) Second not enabled, maintains value On High Clk, second latch enabled First latch not enabled, maintains value ECE/CS 25 42

43 Flip-Flop latch E latch E latch E latch E C C No possibility of races anymore Even if I put 2 FFs back-to-back By the time signal gets through 2 nd latch of st FF st latch of 2 nd FF is disabled Still must ensure signals reach FF before clk rises Important concern in logic design making timing ECE/CS 25 43

44 Flip-Flop Could also trigger on falling edge Switch which latch has NOT on clk Flip-flop is ubiquitous Typically people just say latch and mean FF Which edge: doesn t matter As long as consistent in entire design We ll use rising edge ECE/CS 25 44

45 flip flops Generally don t draw clk input Have one global clk, assume it goes there Often see > as symbol meaning clk FF Maybe have explicit enable > Might not want to write every cycle If no enable signal shown, implies always enabled FF FF E Get output and NOT(output) for free ECE/CS 25 45

46 More Storage Than a -FF: Register File A MIPS register can be made with 32 flip flops One register can store one 32-bit value So do we just replicate this 32 times to get the 32 registers for a MIPS processor? Not exactly Register File (the physical storage for the regs) MIPS register file has bit registers How do we build a Register File using Flip-Flops? What other components do we need? ECE/CS 25 46

47 Register File esign Use a mux to pick read? 32-input mux = slow (other regs not pictured) 32 bit reg E 32 bit reg E 32 bit reg E 32 bit reg E ECE/CS 25 47

48 Register File esign Use a mux to pick read? 32 input mux = slow other regs not pictured Writing the registers Wrata Need to pick which reg Have reg num (e.g., 9) Need to make En9= En, En, = En En 32 bit reg E 32 bit reg E 32 bit reg En3 E 32 bit reg En3 E ECE/CS 25 48

49 First: A ecoder First task: convert binary number to one hot N bits in 2 N bits out 2 N - bits are, bit (matching the input) is 3 ecoder ECE/CS 25 49

50 ecoder Logic ecoder comprised of AN gates for each output: Out = only if input In Out In In 2 3-input gates are fine. In theory, gates can have any # of inputs In practice >4 converted to multiple gates ECE/CS 25 5

51 ecoder Logic ecoder comprised of AN gates for each output: Out = only if input Out In Out In In 2 Repeat for all outputs: AN together right bits (gets messy fast on a slide) ECE/CS 25 5

52 Register File Now we know how to write: Use decoder to convert reg # to one hot Send write data to all regs Use one hot encoding of reg # to enable right reg How do we read? 32-input mux is not realistic To do this: expand our world from {, } to {,, Z} ECE/CS 25 52

53 Kind of like water in a pipe To understand Z, let s make an analogy Think of a wire as a pipe Has water = Has water = This wire is (it has no water) ECE/CS 25 53

54 Kind of like water in a pipe To understand Z, let s make an analogy Think of a wire as a pipe Has water = Has water = This wire is (it is full of water) ECE/CS 25 54

55 Kind of like water in a pipe To understand Z, let s make an analogy Think of a wire as a pipe Has water = Has water = Suppose a gate drives a onto this wire Think of it as sucking the water out ECE/CS 25 55

56 Kind of like water in a pipe To understand Z, let s make an analogy Think of a wire as a pipe Has water = Has water = Suppose a gate drives a onto this wire Think of it as sucking the water out ECE/CS 25 56

57 Kind of like water in a pipe To understand Z, let s make an analogy Think of a wire as a pipe Has water = Has water = Suppose a gate drives a onto this wire Think of it as sucking the water out ECE/CS 25 57

58 Kind of like water in a pipe To understand Z, let s make an analogy Think of a wire as a pipe Has water = Has water = Suppose a gate drives a onto this wire Think of it as sucking the water out ECE/CS 25 58

59 Kind of like water in a pipe To understand Z, let s make an analogy Think of a wire as a pipe Has water = Has water = Suppose the gate now drives a Think of it as pumping water in ECE/CS 25 59

60 Kind of like water in a pipe To understand Z, let s make an analogy Think of a wire as a pipe Has water = Has water = Suppose the gate now drives a Think of it as pumping water in ECE/CS 25 6

61 Kind of like water in a pipe To understand Z, let s make an analogy Think of a wire as a pipe Has water = Has water = Suppose the gate now drives a Think of it as pumping water in ECE/CS 25 6

62 Remember this rule? Remember I told you not to connect two outputs? a b c d BA! If one gate tries to drive a and the other drives a One pumps water in.. The other sucks it out Except it s electric charge, not water Short circuit! lots of current! lots of heat ECE/CS 25 62

63 So this third option: Z There is a third possibility: Z ( high impedance ) Neither pushing water in, nor sucking it out Simply prevents water flow with no effect on pipe Prevents electricity from flowing through Gate that gives us {,,Z} : Tri-state E E - Z ECE/CS 25 63

64 We ve had this rule one day and you break it It s ok to connect multiple outputs together Under one circumstance: All but one must be outputting Z at any time n- n-2 E n- E n-2 E E ECE/CS 25 64

65 Mux, implemented with tri-states We can build effectively a mux from tri-states Much more efficient for large #s of inputs (e.g., 32) 5 ecoder 32 bit reg E 32 bit reg E 32 bit reg E 32 bit reg E ECE/CS 25 65

66 Ports Read Port(s) Ability to do one read per clock cycle Adding a read port Another decoder Another set of tri-states Another output bus (wire connecting the tri-states) Read 2 source registers per instr? Maybe even more if we do many instrs at once Write Port Ability to do one write per cycle Adding a write port Add muxes to select write values ECE/CS 25 66

67 Minor etail FYI: This is not how a register file is implemented (Though it is how other things are implemented) Actually done with SRAM We ll see that later this semester ECE/CS 25 67

68 Summary Can layout logic to compute things Add, subtract, Now can store things flip-flops Registers Also understand clocks Just about ready to make a datapath! ECE/CS 25 68