SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR

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1 OCTAL D-TYPE FLIP-FLOP WITH CLEA SDLS090 OCTOBE 9 EVISED MACH 9 Contains Eight Flip-Flops With Single-ail Outputs Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage egisters Shift egisters Pattern Generators description These monolithic, positive-edge-triggered flipflops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect ar the output. These flip-flops are guaranteed to respond to clock frequencies ranging form 0 to 0 megahertz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 9 milliwatts per flip-flop for the 2 and 0 milliwatts for the LS2. SN42, SN4LS2...J O W PACKAGE SN42...N PACKAGE SN4LS2... DW O N PACKAGE (TOP VIEW) 2Q CL Q 2Q GND V CC Q D D Q Q D D Q CLK SN4LS2... FK PACKAGE (TOP VIEW) Q CL GND CLK Q V CC D Q D D Q Q D FUNCTION TABLE (each flip-flop) logic symbol INPUTS OUTPUT CLEA CLOCK D Q L X X L H H H H L L H L X Q0 CL CLK D D D D 4 4 EN Q 2Q Q Q Q Q This symbol is in accordance with ANSI/IEEE Std and IEC Publication -2. Pin numbers shown are for the DW, J, N, and W packages. PODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 9, Texas Instruments Incorporated POST OFFICE BOX 0 DALLAS, TEXAS 2

2 OCTAL D-TYPE FLIP-FLOP WITH CLEA SDLS090 OCTOBE 9 EVISED MACH 9 schematics of inputs and outputs 2 EQUIVALENT OF EACH INPUT eq TYPICAL OF ALL OUTPUTS 00 Ω NOM INPUT OUTPUT Clear: eq = kω NOM Clock: eq = kω NOM All other inputs: eq = kω NOM LS2 EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS 20 Ω NOM 20 kω NOM INPUT OUTPUT logic diagram (positive logic) CLOCK 4 D D 4 D D CLEA 2 Q 2Q Pin numbers shown are for the DW, J, N, and W packages. 9 2 Q Q Q 9 Q 2 POST OFFICE BOX 0 DALLAS, TEXAS 2

3 OCTAL D-TYPE FLIP-FLOP WITH CLEA SDLS090 OCTOBE 9 EVISED MACH 9 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) NOTE : Supply voltage, V CC (see Note ) V Input voltage V Operating free-air temperature range, T A : SN C to 2 C SN C to 0 C Storage temperature range C to 0 C Voltage values are with respect to network ground terminal. recommended operating conditions SN42 SN42 MIN NOM MAX MIN NOM MAX Supply voltage, V High-level output current, IOH µa Low-level output current, IOL ma Clock frequency, fclock MHz Width of clock or clear pulse, tw.. ns Setup time, tsu Data input Clear inactive state 2 2 Data hold time, th ns Operating free-air temperature, TA C The arrow indicates that the rising edge of the clock pulse is used for reference. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) UNIT PAAMETE TEST CONDITIONS MIN TYP MAX UNIT VIH High-level input voltage 2 V VIL Low-level input voltage 0. V VIK Input clamp voltage = MIN, II = 2 ma. V VOH VOL High-level output voltage Low-level output voltage = MIN, VIL = 0. V, = MIN, VIL = 0. V, VIH = 2 V, IOH = 00 µa VIH = 2 V, IOH = ma ns V 0.4 V II Input current at maximum input voltage = MAX, VI =. V ma IIH IIL High-level input current Low-level input current Clear Clock or D Clear Clock or D = MAX, VI =24V 2.4 = MAX, VI =04V 0.4 IOS Short-circuit output current = MAX ma ICC Supply current = MAX, See Note ma For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at = V, TA = 2 C. Not more than one output should be shorted at a time. NOTE 2: With all outputs open and 4. V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4. V, is applied to clock µa ma POST OFFICE BOX 0 DALLAS, TEXAS 2

4 OCTAL D-TYPE FLIP-FLOP WITH CLEA SDLS090 OCTOBE 9 EVISED MACH 9 switching characteristics, V CC = V, T A = 2 C PAAMETE TEST CONDITIONS MIN TYP MAX UNIT fmax Maximum clock frequency 0 40 MHz tphl Propagation delay time, high-to-low-level output from clear CL = pf, 2 ns L = 400 Ω, tplh Propagation delay time, low-to-high-level output from clock See Note 2 ns tphl Propagation delay time, high-to-low-level output from clock 2 ns NOTE : Load circuits and voltage waveforms are shown in Section. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC (see Note ) V Input voltage V Operating free-air temperature range, T A : SN4LS C to 2 C SN4LS C to 0 C Storage temperature range C to 0 C NOTE : Voltage values are with respect to network ground terminal. recommended operating conditions SN4LS2 SN4LS2 MIN NOM MAX MIN NOM MAX UNIT Supply voltage, V High-level output current, IOH µa Low-level output current, IOL 4 ma Clock frequency, fclock MHz Width of clock or clear pulse, tw ns Setup time, tsu Data input Clear inactive state 2 2 ns Data hold time, th ns Operating free-air temperature, TA C The arrow indicates that the rising edge of the clock pulse is used for reference. 4 POST OFFICE BOX 0 DALLAS, TEXAS 2

5 OCTAL D-TYPE FLIP-FLOP WITH CLEA SDLS090 OCTOBE 9 EVISED MACH 9 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PAAMETE TEST CONDITIONS SN4LS2 SN4LS2 MIN TYP MAX MIN TYP MAX VIH High-level input voltage 2 2 V VIL Low-level input voltage V VIK Input clamp voltage = MIN, II = ma.. V VOH VOL II High-level output voltage Low-level output voltage Input current at maximum input voltage = MIN, VIL = VILmax, VIH = 2 V, IOH = 400 µa UNIT V = MIN, VIH = 2 V, IOL = 4 ma VIL = VILmax, IOL = ma = MAX, VI = V ma IIH High-level input current = MAX, VI = 2. V µa IIL Low-level input current = MAX, VI = 0.4 V ma IOS Short-circuit output current = MAX ma ICC Supply current = MAX, See Note ma For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at = V, TA = 2 C. Not more than one output should be shorted at a time and duration of short circuit should not exceed one second. NOTE 2: With all outputs open and 4. V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4. V, is applied to clock. switching characteristics, V CC = V, T A = 2 C PAAMETE TEST CONDITIONS MIN TYP MAX UNIT fmax Maximum clock frequency 0 40 MHz tphl Propagation delay time, high-to-low-level output from clear CL = pf, 2 ns L =2kΩ kω, tplh Propagation delay time, low-to-high-level output from clock See Note 2 ns tphl Propagation delay time, high-to-low-level output from clock 2 ns NOTE : Load circuits and voltage waveforms are shown in Section. V POST OFFICE BOX 0 DALLAS, TEXAS 2

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