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2 PAGE 2 OF 22 DOCUMENT REVISION HISTORY 1: DOCUMENT REVISION FROM TO DATE DESCRIPTION CHANGED BY A First Release. PHILIP CHENG CHECKED BY PHILIP HO

3 PAGE 3 OF 22 CONTENTS Page No. 1. GENERAL DESCRIPTION 4 2. MECHANICAL SPECIFICATIONS 4 3. INTERFACE SIGNALS 7 4. ABSOLUTE MAXIMUM RATINGS ELECTRICAL MAXIMUM RATINGS - FOR IC ONLY ENVIRONMENTAL CONDITION 9 5. ELECTRICAL SPECIFICATIONS TYPICAL ELECTRICAL CHARACTERISTICS TIMING SPECIFICATIONS POWER SUPPLY SETTING FLOW POWER ON/OFF SEQUENCE UNCONTROLLED POWER OFF REGISTER SETTING FLOW (REGISTER-CONTENT INTERFACE MODE ONLY) OPTICAL CHARACTERISTICS REMARK 22

4 PAGE 4 OF 22 VARITRONIX LIMITED 1. General Description Preliminary Specification of LCD Module Type Model No.: COG-T220MCQA (diagonal), 240 x RGB x 320 dots, 262k colors, transmissive, QVGA-TFT LCD module. Viewing angle: 12 o clock. Driving IC: HIMAX HX8346A TFT controller driver or equivalent. Parallel interface with I80-system or M68-system. Logic voltage: 2.8V(typ.). White LED05 backlight. FPC connection. 2. Mechanical Specifications The mechanical detail is shown in Fig. 1 and summarized in Table 1 below. Table 1 Parameter Specifications Unit Outline dimensions 40.4(W) x 55.3(H) x 3.6(D) (Exclude FPC, bending area, component area, pull mm tape and cable of backlight) Active area 33.48(W) x 44.64(H) mm Display format 240 x RGB x 320 dots Color TFT Color configuration RGB stripes - 240xRGBx (RGB)(W) x (H) Dot size mm (or (W) x (H)) Weight TBD grams

5 PAGE 5 OF 22 Figure 1: Outline Drawing

6 PAGE 6 OF COG-T220MCQA "(DIAGRONAL) QVGA-TFT LCD DISPLAY 240 x RGB x 320 DOTS 240 x RGB VCC VCI GND CS RS WR RD DB0~DB17 RESET BS1 BS0 P68 18 TFT CONTROLLER DRIVER 'HIMAX' HX8346A (COG) A1 WHITE LED05 BACKLIGHT A2 A3 K Figure 2: Block Diagram

7 PAGE 7 OF Interface signals Table 2(a): Pin assignment Pin No. Symbol Description 1 VCC VCC(or IOVCC). Digital circuit power supply. 2 VCI Analog power supply. 3 4 GND GND(or VSSD or VSSA). Digital ground and analog ground. GND = 0V. 5 CS 6 RS 7 WR 8 RD 9 DB0 10 DB1 11 DB2 12 DB3 13 DB4 14 DB5 15 DB6 16 DB7 17 DB8 18 DB9 19 DB10 20 DB11 21 DB12 22 DB13 23 DB14 24 DB15 25 DB16 26 DB17 27 RESET CS (or NCS). Chip select signal. Low: chip can be accessed; High: chip cannot be accessed. RS(or DNC_SCL).The signal for command or parameter select under parallel mode(i.e. Not serial interface): Low: command. High: parameter. WR (or NWR_RNW). I80 system: Serves as a write signal and writes data at the rising edge. M68 system: 0: Write, 1: Read. RD(or NRD_E). I80 system: Serves as a read signal and read data at the low level. M68 system: 0: Read/Write disable, 1: Read/Write enable. DB17~DB0 (or D17~0). 18-bit bi-directional data bus for system interface. 16-bit bus: use DB15~DB0 and DB17~DB16 unused. 18-bit bus: use DB17~DB0. RESET (or NRESET). Reset pin. Setting either pin low initializes the LSI. Must be reset after power is supplied.

8 PAGE 8 OF 22 Pin No. Symbol 28 BS1 29 BS0 Table 2(b): Pin assignment Description Select the MPU interface mode as listed below P68 BS1 BS0 Interface mode DB pins Remark bit bus interface, DB17~DB16: Unused, Default 80-system,64K-Color DB15~DB0: Data setting bit bus interface, DB17~DB16: Unused, 80-system,262K-Color DB15~DB0: Data bit bus interface, 80-system,262K-Color DB17~DB0: Data bit bus interface, DB17~DB8: Unused, 80-system,16M-Color DB7~DB0: Data bit bus interface, DB17~DB16: Unused, 68-system,64K-Color DB15~DB0: Data bit bus interface, DB17~DB16: Unused, 68-system,262K-Color DB15~DB0: Data bit bus interface, 68-system,262K-Color DB17~DB0: Data bit bus interface, DB17~DB8: Unused, 68-system,16M-Color DB7~DB0: Data Note: P68 Input signal format selection 0 Format for I80 series MPU 1 Format for M68 series MPU 30 P68 BS1 BS0 Interface Transferring method of RAM data Transferring method of command Remark bit system interface 16-bit collective 8-bit collective Default setting bit system interface 16-bit + 2 bit 8-bit collective bit system interface 18-bit collective 8-bit collective bit system interface 8-bit + 8-bit + 8-bit 8-bit collective Remark: BS1 pin is set by hardware. 31 A1 Anode of LED1 chip in LED backlight. 32 A2 Anode of LED2 chip in LED backlight. 33 A3 Anode of LED3 chip in LED backlight. 34 K Cathode of LED backlight.

9 PAGE 9 OF Absolute Maximum Ratings 4.1 Electrical Maximum Ratings for IC Only Table 3 Parameter Symbol Min. Max. Unit Note Power supply voltage VCC (or IOVCC) V Input voltage Vi -0.3 VCC V Note: 1.VDD(VCC), GND(VSSD) must be maintained. 2.The modules may be destroyed if they are used beyond the absolute maximum ratings. 4.2 Environmental Condition Item Operating temperature (Topr) Table 4 Storage temperature (Tstg) (Note 1) Remark Min. Max. Min. Max. Ambient temperature -10 C +70 C -20 C +70 C Dry Humidity (note 1) 90% max. RH for Ta 40 C < 50% RH for 40 C < Ta Maximum operating temperature Vibration (IEC ) Frequency: Hz cells must be mounted Amplitude: 0.75 mm on a suitable connector Duration: 20 cycles in each direction. Shock (IEC ) Half-sine pulse shape Pulse duration: 11 ms Peak acceleration: 981 m/s 2 = 100g Number of shocks: 3 shocks in 3 mutually perpendicular axes. Note 1: Product cannot sustain at extreme storage conditions for long time. No condensation 3 directions 3 directions

10 PAGE 10 OF Electrical Specifications 5.1 Typical Electrical Characteristics At Ta = 25 C, VCC= 2.8V±0.5V, GND=0V. Table 5 Parameter Symbol Conditions Min. Typ. Max. Unit Supply voltage (logic) VCC-GND V Supply voltage (analog) VCI V TFT gate ON voltage VGH(Note 2) V TFT gate OFF voltage VGL(Note 3) At Ta=25 C±5 C V TFT common electrode VcomH (Note 4) V voltage VcomL V Supply current ICC VCC=2.8V ma VLED Supply voltage of white =V A1K LED05 backlight =V A2K Forward current V =V A3K I A1 +I A2 +I A3 Luminance =60 ma (on the backlight surface) cd/m 2 Luminance Number of LED dies (on the module surface) = cd/m 2 Colour coordinate of white X LED05 backlight Y Note (1): There is tolerance in optimum LCD driving voltage during production and it will be within the specified range. Note (2): VGH is TFT Gate operating voltage. Note (3): VGL is TFT Gate operating voltage. The low voltage level VGL signal must be fluctuates with same phase as Vcom in case of Cadd (Storage on Gate) structure. Note (4): Vcom must be adjusted to optimize display quality. Note (5): RESET (NRESET) and DB17~DB0 (D17~0)

11 PAGE 11 OF Timing Characteristics Parallel Interface Characteristics (8080-series MPU) At Ta = -10 C to 70 C, GND=VSSA=0V, VCC=2.3V to 2.5V, VCI=2.3V to 2.9V. Table 6 NOTE: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDD1 for Input signals. Figure 3: Parallel Interface Characteristics (8080-series MPU) Figure 4

12 PAGE 12 OF 22 Figure 5: Chip select timing Figure 6: Write to read and read to write timing

13 PAGE 13 OF Parallel Interface Characteristics (6800-series MPU) At Ta = -10 C to 70 C, GND=VSSA=0V, VCC=2.3V to 2.5V, VCI=2.3V to 2.9V. Table 7 NOTE: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDD1 for Input signals. Figure 7: Parallel Interface Characteristics (6800-series MPU) Figure 8

14 PAGE 14 OF Reset Input Timing Table 8 Figure 9: Reset Input Timing

15 PAGE 15 OF Power Supply Setting Flow Figure 10: Power Supply Setting Flow

16 PAGE 16 OF POWER ON/OFF SEQUENCE VCC, VCI can be applied in any order. VCC and VCI can be powered down in any order. During power off, if LCD is in the Sleep Out mode, VCC and VCI must be powered down minimum 120msec after NRESET has been released. During power off, if LCD is in the Sleep In mode, VCC or VCI can be powered down minimum 0msec after NRESET has been released. NCS can be applied at any timing or can be permanently grounded. NRESET has priority over NCS. There will be no damage to the display module if the power sequences are not met. There will be no abnormal visible effects on the display panel during the Power On/Off Sequences. There will be no abnormal visible effects on the display between end of Power On Sequence and before receiving Sleep Out command. Also between receiving Sleep In command and Power Off Sequence. If NRESET line is not held stable by host during Power On Sequence as defined, then it will be necessary to apply a Hardware Reset (NRESET) after Host Power On Sequence is complete to ensure correct operation. Otherwise function is not guaranteed. The power on/off sequence is illustrated below: Case 1 NRESET line is hold High or Unstable by Host at Power On If NRESET line is held high or unstable by the host during Power On, then a Hardware Reset must be applied after both VCI and VCC have been applied - otherwise correct functionality is not guaranteed. There is no timing restriction upon this hardware reset. Figure 11: Case 1 NRESET line is hold High or Unstable by Host at Power On

17 PAGE 17 OF Case 2 NRESET line is held Low by host at Power On If NRESET line is held Low (and stable) by the host during Power On, then the NRESET must be held low for minimum 10µsec after both VCI and VCC have been applied. Figure 12: Case 2 NRESET line is held Low by host at Power On 5.5 UNCONTROLLED POWER OFF The uncontrolled power off means a situation when e.g. there is removed a battery without the controlled power off sequence. There will not be any damages for the display module or the display module will not cause any damages for the host or lines of the interface. At an uncontrolled power off the display will go blank and there will not be any visible effects within 1 second on the display (blank display) and remains blank until Power On Sequence powers it up.

18 PAGE 18 OF Register Setting Flow (Register-Content Interface mode only) The following are the sequences of register setting flow that applied to the HX8346-A driving the TFT display, when operate in Register-Content interface mode Display On/Off Setting flow Figure 13: Display On/Off Setting Sequence

19 PAGE 19 OF Standby Mode Setting Flow Figure 14: Standby Mode Setting Sequence Note: HX8346-A doesn t have the Sleep mode in Register-Content interface mode.

20 PAGE 20 OF Optical Characteristics Table 9: Optical specifications(light source: C light,using TN LC+Polarizer,reference only) Specifications Item s Symbol Condition Unit Note Min. Typ. Max. Transmittance T% % Contrast Ratio CR TR ms Response Time Data are based on TF ms following XR Red Viewing condition YR normal angle 12 o clock XG NTSC: 58% Green θ = φ = 0 YG LC: 5091 Chromaticity XB Light: C light Blue YB (Machine:BM5A) XW Normal Polarizer White YW Without DBEF φ1(3 o clock) Reference Only Hor. Viewing φ2(9 o clock) Center deg. angle θ2(12 o clock) CR Ver. θ1(6 o clock) Note (1) Definition of Contrast Ratio (CR): The contrast ratio can be calculated by the following expression. Contrast Ratio (CR) = L63 / L0 L63: Luminance of gray level 63 L0: Luminance of gray level 0 CR = CR (10) CR (X) is corresponding to the Contrast Ratio of the point X at Figure in Note (5). Note (2) Definition of Response Time (TR, TF): Figure 15

21 PAGE 21 OF 22 Note(3) Definition of Viewing Angle Figure 16 Note (4) Measurement Set-Up: The LCD module should be stabilized at a given temperature for 20 minutes to avoid abrupt temperature change during measuring. In order to stabilize the luminance, the measurement should be executed after lighting Backlight for 20 minutes in a windless room. Note (5): Figure 17 Figure 18

22 PAGE 22 OF Remark "Varitronix Limited reserves the right to change this specification." Tel:(852) Fax:(852) URL: - END -

DATE DESCRIPTION CHANGED BY. CHECKED BY FROM TO A First Release. ZENG LI HUANG YUAN LIANG

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