18 Nov 2015 Testing and Programming PCBA s. 1 JTAG Technologies
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1 8 Nov 25 Testing and Programming PCBA s JTAG Technologies
2 The importance of Testing Don t ship bad products to your customers, find problems before they do. DOA s (Death On Arrival) lead to huge costs ( rule of ten applies) The "rule of ten" specifies that it costs times more to find and fix a defect at the next stage of assembly. Important to find defects in an early stage. 2 JTAG Technologies
3 Each assembly step adds possible defects Apply solder paste 3 JTAG Technologies
4 Each assembly step adds possible defects Pick and place components 4 JTAG Technologies
5 Each assembly step adds possible defects Soldering in reflow oven 5 JTAG Technologies
6 Important statement Simplified statement: If all components on a PCB are soldered correctly - the board should work. Assuming: Design is right Components are OK (ppm -.ppm) Conclusion: Testing the interconnections should be sufficient to detect a great deal of bad boards. 6 JTAG Technologies
7 Defect analysis on real production data Tombstoning Others 6% 3% 26% Shorts incl. SA/SA Component defect 7% Careless placement % Upside down 9% 2% Not placed 7% Opens 7 JTAG Technologies
8 Commonly used Testmethods Structural Test Checks the structure of the board (component placement, soldering, value etc.) Functional Test Checks the functionality of the board 8 JTAG Technologies
9 AOI, Automated Optical Inspection Tombstoning 9 JTAG Technologies
10 AXI, Automated X-ray Inspection JTAG Technologies
11 FP, Flying Probe JTAG Technologies
12 ICT, In Circuit Test Unit under test, UUT Bed of nails Test fixture 2 JTAG Technologies
13 FT, Functional Test Rack and Stack Instrumentation controlled by a computer and dedicated software. Instrumentation: Programmable Power Supplies Generator Oscilloscope Waveform-analyzer Switching matrix etc. 3 JTAG Technologies
14 Pros & Cons Functional Test Functional Test Checks the functionality of the board - Big problem if the core is not running - Manual creation of the tests - Very difficult to diagnose, doesn t pinpoint to the exact location of the problem - Requires highly skilled engineers to find the problem - Time consuming - Expensive test 4 JTAG Technologies
15 Pros & Cons Structural Test Structural Test Checks the structure of the board (interconnects, device orientation, device values etc.) - test + Automatic generation based on the Netlist + Low cost + Pinpoints to the exact location of the problem if sufficient testpoints are available 5 JTAG Technologies
16 Interconnect test on a PCBA with BGA s The probes require a minimum clearance, and a typical spring force of -2g per pin to ensure good contact. 6 JTAG Technologies
17 Boundary-scan provides accessibility What is Boundary-scan and how does it work Official standard: IEEE Std JTAG Technologies
18 Boundary-scan architecture The Boundary-scan architecture is a standard implementation in many devices, such as µs, DSPs, FPGAs etc.. I/ I/ I/ I/ I/ I/ I/ I/ I/ 8 JTAG Technologies
19 Boundary-scan architecture Additional Testlogic and pins have been added to the device I/ I/ I/ I/ I/ BSR Boundary-Scan Register I/ I/ I/ I/ Bypass TMS TCK TRST Optional Instruction register 9 JTAG Technologies Test Data In Test Data Out TMS Test Mode Select TCK Test Clock TRST Test Reset (optional)
20 Goal is to test the solder joints Component soldered onto a PCB. Goal is to find possible detects. TMS TCK Bypass Instruction register 2 JTAG Technologies
21 Shift-in the predefined testvector via Testvector Bypass TMS TCK TRST Optional Instruction register Via the testvector is Shifted into the BSR. TCK defines the rate. 2 JTAG Technologies
22 Repeat Shift-in operation Testvector -> Bypass Shift TMS TCK TRST Optional Instruction register 22 JTAG Technologies
23 Repeat Shift-in operation Testvector Bypass Shift TMS TCK TRST Optional Instruction register 23 JTAG Technologies
24 Repeat Shift-in operation Testvector Bypass Shift TMS TCK TRST Optional Instruction register 24 JTAG Technologies
25 Repeat Shift-in operation Testvector Bypass Shift TMS TCK TRST Optional Instruction register 25 JTAG Technologies
26 Repeat Shift-in operation Testvector Bypass Shift TMS TCK TRST Optional Instruction register 26 JTAG Technologies
27 Repeat Shift-in operation Testvector Bypass Shift TMS TCK TRST Optional Instruction register 27 JTAG Technologies
28 Repeat Shift-in operation Testvector Bypass Shift TMS TCK TRST Optional Instruction register 28 JTAG Technologies
29 Repeat Shift-in operation Testvector Bypass Shift TMS TCK TRST Optional Instruction register 29 JTAG Technologies
30 Repeat Shift-in operation Testvector Bypass Notice that during the shift operation the pins don t change state. Shift TMS TCK TRST Optional Instruction register 3 JTAG Technologies
31 UPDATE command With the Update command the data from the BSR is driven onto the pins. Update TMS TCK TRST Optional Bypass Instruction register If the pins are soldered correctly the values on the nets are equal to the values on the pins. 3 JTAG Technologies
32 Sense the values on the pins. Let s assume that these values are on the nets. Bypass TMS TCK TRST Optional Instruction register 32 JTAG Technologies
33 CAPTURE senses the values on the pins Bypass Capture TMS TCK Instruction register 33 JTAG Technologies
34 . and puts them into the BSR With the Capture command the data on the pins is copied into the BSR. Bypass Capture TMS TCK TRST Optional Instruction register 34 JTAG Technologies
35 Shift-out captured data via Bypass Shifted-out Shift TMS TCK TRST Optional Instruction register 35 JTAG Technologies
36 Repeat Shift-out operation Bypass Shifted-out Shift TMS TCK TRST Optional Instruction register 36 JTAG Technologies
37 Repeat Shift-out operation Bypass Shifted-out Shift TMS TCK TRST Optional Instruction register 37 JTAG Technologies
38 Repeat Shift-out operation Bypass Shifted-out Shift TMS TCK TRST Optional Instruction register 38 JTAG Technologies
39 Repeat Shift-out operation Bypass Shifted-out Shift TMS TCK TRST Optional Instruction register 39 JTAG Technologies
40 Repeat Shift-out operation Bypass Shifted-out Shift TMS TCK TRST Optional Instruction register 4 JTAG Technologies
41 Repeat Shift-out operation Bypass Shifted-out Shift TMS TCK TRST Optional Instruction register 4 JTAG Technologies
42 Repeat Shift-out operation Bypass Shifted-out Shift TMS TCK TRST Optional Instruction register 42 JTAG Technologies
43 Compare result with Expected value Remember that the expected value equals the values on the nets at the moment they got captured Bypass Expected Result TMS TCK TRST Optional Instruction register Mismatch 43 JTAG Technologies
44 Pinpoint to faulty pins In this example the mismatch is due to these Open pins. Bypass Expected Result TMS TCK TRST Optional Instruction register Mismatch 44 JTAG Technologies
45 Simple board with two Bscan devices What are the required steps to test Test the interconnections in the following example. 45 JTAG Technologies
46 Multiple Bscan devices can be cascaded IC IC2 BP IR BP IR TMS TCK from IC is connected to of IC2, Bscan chains may be cascaded 46 JTAG Technologies
47 Interconnection test IC IC2 BP IR BP IR TMS TCK Goal is to test the circled interconnections 47 JTAG Technologies
48 Step. Define testvector IC IC2 BP IR BP IR TMS TCK In this example an arbitrary testvector xxxx is used. 48 JTAG Technologies
49 Step 2. Shift-in testvector IC IC2 BP IR BP IR SHIFT TMS TCK The repeated SHIFT command shifts-in the testvector into the BSR. 49 JTAG Technologies
50 Step 3. send UPDATE command IC BP IR IC2 BP IR UPDATE TMS TCK Send the UPDATE command over TMS, the testvector is driven onto the corresponding pins of IC. If the pins are soldered correctly the value will also appear on the nets. 5 JTAG Technologies
51 Step 4. Send Capture command IC BP IR IC2 BP IR CAPTURE TMS TCK The CAPTURE command senses the data on the pins and puts the value in the corresponding cells 5 JTAG Technologies
52 Step 5. Shift-out captured data IC IC2 BP IR BP IR Result SHIFT TMS TCK The repeated SHIFT command shifts-out the captured vector. 52 JTAG Technologies
53 Step 5. Shift-out captured data IC IC2 Expected BP IR BP IR Result TMS TCK The repeated SHIFT command shifts-out the captured vector. 53 JTAG Technologies
54 Step 6. Compare result with expected value IC IC2 Expected BP IR BP IR Result TMS TCK Mismatch caused by an open pin Compare result with the expected value. 54 JTAG Technologies
55 Compare and Diagnose Errors are shown in inverse video. In this case the result was a however a was expected. and are for Input H, L and Z are for output The diagnostics pinpoints to the exact error locations 55 JTAG Technologies
56 Faultdetection With the aid of Intelligent testvectors Opens Shorts SA and SA problems are easily detected The Intelligent testvectors are based on an Enhanced Binary Search principle. (Minimum set of Testvectors with a Maximum Testcoverage) 56 JTAG Technologies
57 Testing Non-Bscan components Bscan Non-Bscan Bscan Boundary-scan chain 57 JTAG Technologies
58 Testing connectivity of NAND Gate A B & Y Bscan A B Y Boundary-scan chain 58 JTAG Technologies Bscan Use Truthtable to stimulate the inputs and sense the outputs of the NAND-gate using the Bscan cells. A model contains information about the Truthtable.
59 Testing connectivity of RAM ADD Bscan RAM DATA Bscan Ctrl Boundary-scan chain Stimulate the Add/Data/Ctrl pins to write and read data from the RAM. The information on how to read/write to the memory is described in a model. 59 JTAG Technologies
60 Testing connectivity of FLASH ADD Bscan FLASH DATA Bscan Ctrl Boundary-scan chain A FLASH model contains all the information on how to get access to the device. 6 JTAG Technologies
61 Programming external FLASH ADD Bscan FLASH DATA Bscan Ctrl Boundary-scan chain The Image file gets integrated into the Bscan patterns to program the FLASH. 6 JTAG Technologies
62 Testing connectivity I/O block and Connector Bscan Bscan I/O Connector LoopBack Connector Boundary-scan chain Use loopback connector to test the connectivity of the I/O block and Connector 62 JTAG Technologies
63 Testing connectivity I/O block and Connector Bscan Bscan I/O Connector External Bscan device/board Boundary-scan chain Use an external Bscan device/board with required # of I/O pins to get full access. 63 JTAG Technologies
64 Testing connectivity serial devices I2C, SPI etc. SDA SLC Bscan I2C Bscan Simulating the I2C protocol on SDA and SLC givess access to the I2C device The information on how to simulate the serial protocol is defined in a model. 64 JTAG Technologies
65 Programming via the JTAG interface We ve already seen that the Boundary-scan chain can be used for Programming an External Flash. Some devices use the JTAG interface to get direct access to the inside of the device for programming/debug purposes. 65 JTAG Technologies
66 Programming FPGA s etc. Logic cells Interconnections JTAG Interface 66 JTAG Technologies
67 Programming FPGA s etc. JTAG Interface FPGAs use the JTAG interface to directly download the configuration file into the device. 67 JTAG Technologies
68 Programming FPGA s etc. JTAG Interface Fortunately, most of these these chips also have a Boundary-scan chain that provides direct access to the I/O pins and can be used for testing. 68 JTAG Technologies
69 Programming Embedded Flash Internal FLASH µ JTAG Interface Many µs have internal flash that can be directly programmed via de JTAG interface 69 JTAG Technologies
70 Warning Not all devices with a JTAG interface are Boundary-scan compliant. JTAG interface JTAG interface For this type of devices a BSDL-file exists For this type of devices NO BSDL-file exists 7 JTAG Technologies
71 What is a BSDL-file The Boundary-Scan Description Language (BSDL) file provides a description of the way in which boundary-scan is implemented in the device device. BSDL is the standard modeling language for boundary-scan devices. BSDL is written within a subset of VHDL. 7 JTAG Technologies
72 How to get BSDL files BSDL files can be downloaded from the suppliers websites Example: 72 JTAG Technologies
73 Example BSDL file 73 JTAG Technologies
74 Example BSDL file 74 JTAG Technologies
75 Demonstration 75 JTAG Technologies
76 Blockdiagram 76 JTAG Technologies
77 Full access via the TAP (Test Access Port) TAP 77 JTAG Technologies
78 JTAG Live Boundary-scan tools JTAG Live Studio is a complete Boundary-scan solution for testing, debugging and programming boards. 78 JTAG Technologies
79 JTAG Live Buzz Buzz is ideal for electronic engineers and technicians to use in checking printed circuit boards for basic continuity and correct operation. FREE download on 79 JTAG Technologies
80 Supported controllers 8 JTAG Technologies
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