Lecture 11: Synchronous Sequential Logic
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1 Lecture 11: Synchronous Sequential Logic Syed M. Mahmud, Ph.D ECE Department Wayne State University Aby K George, ECE Department, Wayne State University
2 Contents Characteristic equations Analysis of clocked sequential circuits State equation, state table and state diagram State reduction and assignment Design procedure Chapter 5 ECE 2610 Digital Logic 1 2
3 Characteristic Tables Chapter 5 ECE 2610 Digital Logic 1 3
4 Characteristic Equations Q + = S + R Q Q + = JQ + K Q Q + = D Q + = T Q Chapter 5 ECE 2610 Digital Logic 1 4
5 Analysis of Clocked Sequential Circuits Obtaining a table or diagram for the time sequence of inputs, outputs, and internal states. Write the Boolean expression that describe the behavior of the sequential circuit. Draw the logic diagram with flip-flops and clock inputs. Logic diagram may or may not include the combinational circuits. Chapter 5 ECE 2610 Digital Logic 1 5
6 State Equation Transition equation Specifies next state as a function of present state and inputs. Example: A t + 1 = A t x t + B t x(t) B t + 1 = A t x t Output equation y t = A t + B t x (t) Chapter 5 ECE 2610 Digital Logic 1 6
7 State Table Time sequence of inputs, outputs, and flip-flops in a tabular form Also called transition table A t + 1 = Ax + Bx B t + 1 = A x y t = A + B x Chapter 5 ECE 2610 Digital Logic 1 7
8 State Diagram Graphical representation of state table Chapter 5 ECE 2610 Digital Logic 1 8
9 Analysis with D Flip-flop Draw the state diagram for the following state equation D A = A x y or A t + 1 = A x y Chapter 5 ECE 2610 Digital Logic 1 9
10 Mealy and Moore Models of Finite State Machines Finite State Machine (FSM) Chapter 5 ECE 2610 Digital Logic 1 10
11 State Reduction Reduction in number of flip-flops in a sequential circuit. m- flip-flops can produce 2 m states. Two states are said to be equivalent, if for each member of the set of inputs, they give exactly same output and send the circuit either to the same stare or to an equivalent state. Chapter 5 ECE 2610 Digital Logic 1 11
12 State Reduction Chapter 5 ECE 2610 Digital Logic 1 12
13 Design Procedure 1. From the word description and specifications of the desired operation, derive a state diagram for the circuit. 2. Reduce the number of states if necessary. 3. Assign binary values to the states. 4. Obtain the binary-coded state table. 5. Choose the type of flip-flops to be used. 6. Derive the simplified flip-flop input equations and output equations. 7. Draw the logic diagram. Chapter 5 ECE 2610 Digital Logic 1 13
14 Excitation Tables for Flip Flops 1. Excitation tables are needed to design a sequential system. 2. These tables can be derived from the characteristic tables of Flip Flops. Characteristic Table for S-R Flip Flop Excitation Table for S-R Flip Flop S R Q Q X X Q Q+ S R X X 0 Chapter 5 ECE 2610 Digital Logic 1 14
15 Excitation Table for J-K Flip Flop Characteristic Table for J-K Flip Flop Excitation Table for J-K Flip Flop J K Q Q Q Q+ J K X X 1 0 X X 0 Chapter 5 ECE 2610 Digital Logic 1 15
16 Excitation Tables for D and T Flip Flops Characteristic Table for D Flip Flop D Q Q Excitation Table for D Flip Flop Q Q+ D Characteristic Table for T Flip Flop T Q Q Excitation Table for T Flip Flop Q Q+ T Chapter 5 ECE 2610 Digital Logic 1 16
17 Example: State diagram from description Draw the state diagram for a Moore Machine that detects a sequence of three or more consecutive 1 s in a stream of bits coming through an input line. Chapter 5 ECE 2610 Digital Logic 1 17
18 Design Example 1: Sequence Detector using D Flip-flop Chapter 5 ECE 2610 Digital Logic 1 18
19 Design Example 1: Sequence Detector using D Flip-flop Chapter 5 ECE 2610 Digital Logic 1 19
20 Design Example 2: Sequential circuit using JK Flip-flop Chapter 5 ECE 2610 Digital Logic 1 20
21 Design Example 2: Sequential circuit using JK Flip-flop Chapter 5 ECE 2610 Digital Logic 1 21
22 Design Example 3: Counter using T Flip-flop Chapter 5 ECE 2610 Digital Logic 1 22
23 Design Example 3: Counter using T Flip-flop Chapter 5 ECE 2610 Digital Logic 1 23
24 Design Example 4: Implement X Flip-flop using Y Flip-flop Design JK flip-flop using T flip-flop J K T T J K KQ n m 0 m 1 m 3 m J m 4 m 5 m 7 m Q n T = KQ n + JQ n Chapter 5 ECE 2610 Digital Logic 1 24
25 Summary How to find the characteristic table, characteristic equation, and excitation table for a flip-flop How to implement a state table, state equation, or state diagram using different flip-flops? What are the design procedure for a state machine? What are the differences between Mealy and Moore FSM? How to do the state reduction? How to design one Flip-flop using other flip-flop? Chapter 5 ECE 2610 Digital Logic 1 25
26 Homework Chapter 5 ECE 2610 Digital Logic 1 26
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Sequential Logic. Analysis and Synthesis. Joseph Cavahagh Santa Clara University. r & Francis. TaylonSi Francis Group. , Boca.Raton London New York \
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