Unit-5 Sequential Circuits - 1

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1 Unit-5 Sequential Circuits With the help of block diagram, explain the working of a JK Master-Slave flip flop. 2. Differentiate between combinational circuit and sequential circuit. 3. Explain Schmitt trigger (July 14) 6 Marks 4. Give transition diagram of JK and T Flip flops. (July 14) 8 Marks 5. Show how a D flip flop converted into JK flipflop (Dec 14 /Jan 15) (July 13) 6 Marks 6. Show how SR flip flop can be converted to a JK flip flop. (Dec 14 /Jan 15)(June/July15)10 Marks 7. Write HDL design of D-Flip flop (Dec 13 /Jan 14) 10 Marks 8. With the help of a neat diagram explain the working of a Master Slave JK flip flop (June/July15) (July 13) 10 Marks 9. What do you mean by characteristic equation of a flip-flop? Derive characteristic equation for SR flip flop (July 13) 10 Marks 10. Write HDL design for JK flip-flop (Dec 13/Jan 14) 10 Marks 11. Implement T flip flop using JK flipflop (Dec 13 /Jan 14) 10 Marks 12.Explain a 4 bit universal shift register in detail and give its timing diagram. 13.With neat timing diagram, explain the working of a 4-bit SISO register. 14.Design a 3 bit PISO(DFlip flop) (July 13)6 marks 15. Design two 4 bit serial adder. (July 13) 6marks 16. Design a 4 bit Johnson counter with sate table. (July 13)8 marks 17.Explain Johnson Counter with neat diagram and timing diagram

2 18.Write verilog code for Shift Register. 19.Give applications of J-K flip-flops. (July14) 10 Marks (July14) 10 Marks 20. Draw the general block diagram of multivibrator.

3 Unit 5 Sequential Circuits With the help of block diagram, explain the working of a JK Master-Slave flip flop. All sequential circuits that we have seen in the last few pages have a problem (All level sensitive sequential circuits have this problem). Before the enable input changes state from HIGH to LOW (assuming HIGH is ON and LOW is OFF state), if inputs changes, then another state transition occurs for the same enable pulse. This sort of multiple transition problem is called racing. If we make the sequential element sensitive to edges, instead of levels, we can overcome this problem, as input is evaluated only during enable/clock edges. In the figure above there are two latches, the first latch on the left is called master latch and the one on the right is called slave latch. Master latch is positively clocked and slave latch is negatively clocked.

4 2. Differentiate between combinational circuit and sequential circuit. Combinational Logic Circuit : The circuit in which outputs depends on only present value of inputs. So it is possible to describe each output as function of inputs by using Boolean expression. No memory element involved. No clock input. Circuit is implemented by using logic gates. The propagation delay depends on, delay of logic gates. Examples of combinational logic circuits are : full adder, subtractor, decoder, codeconverter, multiplexers etc. inputs Combinational Logic Circuit outputs Sequential Circuits : Sequential Circuit is the logic circuit in which output depends on present value of inputs at that instant and past history of circuit i.e. previous output. The past output is stored by using memory device. The internal data stored in circuit is called as state. The clock is required for synchronization. The delay depends on propagation delay of circuit and clock frequency. The examples are flip-flops, registers, counters etc. inputs Combinational Logic Circuit outputs Memory Device

5 3. Explain Schmitt trigger (July 14) 6 Marks The circuit is designed with a positive feedback and hence will have a regenerative action which will make the output switch levels. Also, the use of positive voltage feedback instead of a negative feedback, aids the feedback voltage to the input voltage, instead of opposing it. The use of a regenerative circuit is to remove the difficulties in a zero-crossing detector circuit due to low frequency signals and input noise voltages. 4. Give transition diagram of JK and T Flip flops. (July 14) 8 Marks

6 5. Show how a D flip flop converted into JK flipflop (Dec 14 /Jan 15)(July 13) 6 Marks D Flip Flop to JK Flip Flop In this conversion, D is the actual input to the flip flop and J and K are the external inputs. J, K and Qp make eight possible combinations, as shown in the conversion table below. D is expressed in terms of J, K and Qp. The conversion table, the K-map for D in terms of J, K and Qp and the logic diagram showing the conversion from D to JK are given in the figure below. 6. Show how SR flip flop can be converted to a JK flip flop. (Dec 14 /Jan 15)(June/July15)10 Marks

7 In SR FF, S=R=1 condition is not allowed. JK FF is modified version of SR FF. Due to feedback from output to input AND Gate J=K=1 is toggle condition for JK FF. The output is complement of the previous output. 7. Write HDL design of D and JK Flip flop (Dec 13 /Jan 14) 10 Marks //D flip-flop module D_FF (Q,D,CLK); output Q; input D,CLK; reg Q; CLK) Q = D; endmodule module JK_FF (J,K,CLK,Q,Qnot); output Q,Qnot; input J,K,CLK; reg Q; assign Qnot = ~ Q ; CLK) case({j,k}) 2'b00: Q = Q; 2'b01: Q = 1'b0; 2'b10: Q = 1'b1; 2'b11: Q = ~ Q; endcase endmodule 8. With the help of a neat diagram explain the working of a Master Slave JK flip flop (June/July15) (July 13) 10 Marks All sequential circuits that we have seen in the last few pages have a problem (All level sensitive sequential circuits have this problem). Before the enable input changes state from HIGH to LOW (assuming HIGH is ON and LOW is OFF state), if inputs changes,

8 then another state transition occurs for the same enable pulse. This sort of multiple transition problem is called racing. If we make the sequential element sensitive to edges, instead of levels, we can overcome this problem, as input is evaluated only during enable/clock edges. In the figure above there are two latches, the first latch on the left is called master latch and the one on the right is called slave latch. Master latch is positively clocked and slave latch is negatively clocked. 9. What do you mean by characteristic equation of a flip-flop? Derive characteristic equation for SR flip flop (July 13) 10 Marks A descriptions of the next state table of a flip flop. Constructing from the Karnaugh map for Qt+1 in terms of the present state and input.

9 10. Write HDL design for JK flip-flop (Dec 13/Jan 14) 10 Marks module JK_FF (J,K,CLK,Q,Qnot); output Q,Qnot; input J,K,CLK; reg Q; assign Qnot = ~ Q ; CLK) case({j,k}) 2'b00: Q = Q; 2'b01: Q = 1'b0;

10 2'b10: Q = 1'b1; 2'b11: Q = ~ Q; endcase endmodule 11. Implement T flip flop using JK flipflop (Dec 13 /Jan 14) 10 Marks 12.Explain a 4 bit universal shift register in detail and give its timing diagram.

11 13.With neat timing diagram, explain the working of a 4-bit SISO register. The serial in/serial out shift register accepts data serially--that is, one bit at a time on a single line. It produces the stored information on its output also in serial form. With four stages, this register can store up to four bits of data; its-storage capacity is four bits. 14.Design a 3 bit PISO(DFlip flop) (July 13)6 marks Parallel-in to Serial-out (PISO) Shift Register The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallel-out one above. The data is loaded into the register in a parallel format in which all the data bits enter their inputs simultaneously, to the parallel input pins P A to P D of the register. The data is then read out sequentially in the normal shift-right mode from the register at Q representing the data present at P A to P D. This data is outputted one bit at a time on each clock cycle in a serial format. It is important to note that with this system a clock pulse is not required to parallel load the register as it is already present, but four clock pulses are required to unload the data.

12 4-bit Parallel-in to Serial-out Shift Register 15. Design two 4 bit serial adder. (July 13) 6marks 16. Design a 4 bit Johnson counters with sate table. (July 13)8 marks 4-bit Ring Counter

counter. Like a ring counter a Johnson counter is a shift register fed back on its' self. It requires half the stages of a comparable ring counter for a given division ratio.

13 Truth Table for a 4-bit Johnson Ring Counter 17.Explain Johnson Counter with neat diagram and timing diagram The switch-tail ring counter, also know as the Johnson counter, overcomes some of the limitations of the ring counter. Like a ring counter a Johnson counter is a shift register fed back on its' self. It requires half the stages of a comparable ring counter for a given division ratio. If the complement output of a ring counter is fed back to the input instead of the true output, a Johnson counter results. The difference between a ring counter and a Johnson counter is which output of the last stage is fed back (Q or Q'). Carefully compare the feedback connection below to the previous ring counter.

14 18.Write verilog code for Shift Register. (July14) 10 Marks module shftreg (s1,s0,pin,lfin,rtin,a,clk,clr); input s1,s0; //Select inputs input lfin, rtin; //Serial inputs input CLK,Clr; //Clock and Clear input [3:0] Pin; //Parallel input output [3:0] A; //Register output reg [3:0] A; (posedge CLK or negedge Clr) if (~Clr) A = 4'b0000; else case ({s1,s0}) 2'b00: A = A; //No change 2'b01: A = {rtin,a[3:1]}; //Shift right 2'b10: A = {A[2:0],lfin}; //Shift left //Parallel load input 2'b11: A = Pin; endcase endmodule 19.Give applications of J-K flip-flops. (July14) 4 Marks J-K flip-flops are used in shift registers. 2. J-K flip-flops are used in counters.

15 20. Draw the general block diagram of multivibrator. F1 and F2 are the options for the connections of passive components according to the types of multivibrator to design. For example (a) Astable Multivibrator: F1 = C1 and F2 = C2. (b) Monostable Multivibrator: F1 = C and F2 = R. (c) Bistable Multivibrator : F1 = F2 = Parallel combination of R and C of different values.

PESIT Bangalore South Campus

PESIT Bangalore South Campus SOLUTIONS TO INTERNAL ASSESSMENT TEST 3 Date : 8/11/2016 Max Marks: 40 Subject & Code : Analog and Digital Electronics (15CS32) Section: III A and B Name of faculty: Deepti.C Time : 11:30 am-1:00 pm Note: