DIGIMIMIC Digital/Analog Parts Portfolio

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1 One Company, more solutions DIGIMIMIC Digital/Analog Parts Portfolio

2 Introduction (1) Goal of this presentation is to quickly introduce the customer to DIGIMIMIC company and its digital and analog product family. The DIGIMIMIC core founder team has been span off from one Co-founder (VP of digital product development in iterra LLC) and one Senior Engineer of iterra Communications LLC with the support and blessing of the former mother company. As matter of fact the starting product portfolio was designed and tested by the same DIGIMIMIC technical team in iterra Communications using both GaAs HBT and InP HBT. This product portfolio is currently manufactured, under license agreement, using the iterra Communications LLC mask set. 2

3 Introduction (2) DIGIMIMIC core technical team has also designed fully functional 40G digital dies in InP HBT. The following Slides will give a glance of the parts functionality, aimed to highlight the signal quality achieved at the output of the individual components. 3

4 DM4005 DFF DM GHz Clock Frequency Range 900 mvpp single ended output dynamic Output Rise time (20%-80%) : 25 ps Output Fall time (20%-80%) : 24 ps DC coupled clock input DC coupled data input 50 ohm matched DC coupled data output Low power consumption : V (VQH = 0.0V, VQL = -0.9V) V (VQH = 0.0V, VQL = -0.6V) V (VQH = 0.0V, VQL = -0.4V) DM4005 Eye Diagram 12.5 Gb/s 4

5 DM4021 TFF Gate DM4021 D 100 Ohm D D Q D Q Q Q 100 Ohm Data rate range: DC up to 20 Gb/s NRZ Maximum Clock Frequency as clock divider: 14 GHz 900 mvpp typical single ended output dynamic Input sensitivity: single ended input > 250 mv jitter transfer RMS < 1 ps Output Rise time (20%-80%): < 27 ps Output Fall time (20%-80%): < 24 ps DC or AC coupled data input 50 ohm matched DC coupled data output Differential or single ended inputs Differential or single ended output Full SCFL I/O levels compatibility Low power consumption : 0.71 W DM4021 Eye Diagram 12.5 GHz Clock Input 5

6 DM4011 XOR Gate DM4011 DM4011 Eye Diagram 10.7 Gb/s NRZ Data Input (Edge Detector Application) 6

7 DM ps Phase Delay DM4031 Ultra wideband signal handling: up to 12.5Gb/s NRZ Delay adjustment: up to 100ps 900 mv p-p typical single ended output dynamic jitter RMS: < 1.5ps Output Rise time (20% 80 %): < 23ps Output Fall time (20% 80 %): < 20ps 50Ohm matched DC-coupled inputs 50Ohm matched DC-coupled outputs Differential or single ended I/Os Power consumption: 1.65W DM4031 Shifting 10.7 Gb/s NRZ Data Input 7

8 DM ps Phase Delay +180 Flipper DM4032 Ultra wideband signal handling: up to 12.5Gb/s NRZ Delay adjustment: up to 50ps Flipping capability (180 degrees shift) 900 mv p-p typical single ended output dynamic jitter RMS: < 1.5ps Output Rise time (20% 80 %): < 22ps Output Fall time (20% 80 %): < 20ps 50Ohm matched DC-coupled inputs 50Ohm matched DC-coupled outputs Differential or single ended I/Os Power consumption: 1.15W DM4032 Shifting 12.5 Gb/s NRZ Data Input 8

9 DM4033 Dual Independent 100 ps Phase Delay VEE1 VC1m VC1p VC1ref 50 O hm 60 O hm DIN1 DOUT1 100ps tunable delay CORE1 DIN1/ DOUT1/ 50 O hm 60 Ohm DM4033 it O hm 60 O hm DIN2 DOUT2 100ps tunable delay CORE2 DIN2/ DOUT2/ 50 O hm 60 Ohm Ultra wideband signal handling: up to 12.5Gb/s NRZ Delay adjustment: up to 100ps Dual Independent cores on one single Die 900 mv p-p typical single ended output dynamic jitter RMS: < 1.5ps Output Rise time (20% 80 %): < 21ps Output Fall time (20% 80 %): < 18ps 50Ohm matched DC-coupled inputs 50Ohm matched DC-coupled outputs Differential or single ended I/Os Power consumption: 1.6W (each core) VEE2 VC2m VC2p VC2ref VC1 VEE 1 DIN1 DOU T1 DIN1/ DOUT1/ it4033 DM4033 DIN2 DOU T2 DIN2/ DOU T2 / Fp 0t6x5et Fp 06 t x5et Fp 06 t x5et Fp 06 t x5et VEE 2 VC2 Eye Diagram 12.5 Gb/s NRZ Data Input 9

10 DM4050 LVDS to SCFL 3Gb/s Level Translator VDD VEE it4050 DM4050 DIN1 DOUT1 100 Ohm DIN1/ DOUT1/ DIN2 DOUT2 100 Ohm DIN2/ DOUT2/ VDD1 Wideband signal handling: up to 3.125Gb/s NRZ Input sensitivity: 350mV differential 450 mv p-p typical single ended output dynamic jitter RMS: < 2ps Output Rise time (20% 80 %): < 55ps Output Fall time (20% 80 %): < 55ps 100Ohm (differential) matched DC-coupled inputs 50Ohm matched DC-coupled outputs Differential or single ended Output Power consumption: 140mW per translator VEE1 DIN1 DOUT1 DIN1/ DOUT1/ DM4050 it4050 DIN2 DOUT2 DIN2/ DOUT2/ VEE2 Fp 06 t x5et Fp 0t6x5et VDD2 Eye Diagram 3 Gb/s NRZ Data Input 10

11 DM4051 Rockets I/O to SCFL Level Translator VDD VEE it4051 DM4051 VD D DIN1 DOUT1 DIN1/ DOUT1/ VD D VD D DIN2 DOUT2 DIN2/ DOUT2/ Wideband signal handling: up to 3.125Gb/s NRZ Input sensitivity: 500mV single ended 450 mv p-p typical single ended output dynamic jitter RMS: < 2ps Output Rise time (20% 80 %): < 33ps Output Fall time (20% 80 %): < 33ps 50Ohm matched DC-coupled inputs 50Ohm matched DC-coupled outputs Differential or single ended I/Os Power consumption: 175mW per translator VD D VDD1 VEE1 DIN1 DOUT1 DIN1/ DOUT1/ it4051 DM4051 DIN2 DOUT2 DIN2/ DOUT2/ VEE2 Fp 06t x5et Fp 06 t x5et VDD2 Eye Diagram 3 Gb/s NRZ Data Input 11

12 DM4034 1:2 Power Splitter with 100 ps Phase Delay VEE VC1m VC1p VC1ref it4034 DM O hm 100ps tunable delay 60 O hm DOUT1 DOUT1/ DIN DIN/ 60 O hm 100ps tunable delay 60 O hm DOUT2/ DOUT2 Ultra wideband signal handling: up to 12.5Gb/s NRZ Independent delay adjust on each output: 100ps High Input sensitivity: 300mV single ended 900 mv p-p typical single ended output dynamic jitter RMS: < 1.5ps Output Rise time (20% 80 %): < 20ps Output Fall time (20% 80 %): < 17ps 50Ohm matched DC-coupled inputs 50Ohm matched DC-coupled outputs Differential or single ended I/Os Power consumption: W VC2m VC2p VC2ref VC1 GN D D OU T1 GN D D OUT1/ GN D D IN DM4034 it4034 D IN/ GN D DOU T2/ GN D DO UT2 GN D Fp 06t x5et Fp 06 t x5et Fp 06 t x5et Fp 0t6x5et VE E VC2 Independent Shifting 10.7 Gb/s NRZ Data Input 12

13 DM4035 1:4 Power Splitter VEE OUT1/ OUT1 OUT4/ OUT4 60 Ohm 60 O hm 60 Ohm 60 Ohm DIN DM4035 it4035 DIN/ 60 Ohm 60 O hm 60 Ohm 60 Ohm OUT2/ OUT2 Ultra wideband signal handling: up to 12.5Gb/s NRZ High Input sensitivity: 300mV single ended 900 mv p-p typical single ended output dynamic jitter RMS: < 1.5ps Output Rise time (20% 80 %): < 20ps Output Fall time (20% 80 %): < 17ps 50Ohm matched DC-coupled inputs 50Ohm matched DC-coupled outputs Differential or single ended I/Os Power consumption: 2.0W OUT3/ OUT3 1 uf DOUT4 56 te0 xpt F DOUT4/ DOUT1 pt F te0x 56 1 DOUT1/ uf VEE DIN it4035 DM4035 DIN/ 5 6te 0x pt F DOUT3 DOUT3/ DOUT2 uf DOUT2/ F xpt te uf Eye Diagram 12.5 Gb/s NRZ Data Input 13

14 DM4131 x2 Clock Multiplier (2-4 GHz) DM4131 Clock Input range: from 2 GHz up to 4 GHz 900 mvpp typical single ended output dynamic Input sensitivity: single ended input > 200mV Jitter RMS < 1 ps matched inputs matched outputs (DC) SCFL I/O levels fully compatible Differential or single ended I/Os Duty Cycle control Echo inputs available Power Consumption: 1.4W DM4131 Eye Diagram 2.5 GHz Clock Input 14

15 DM4134 x2 Clock Multiplier (4-7 GHz) DM4134 Clock Input range: from 4 GHz up to 7 GHz 900 mvpp typical single ended output dynamic Input sensitivity: single ended input > 200mV Jitter RMS < 1 ps matched inputs matched outputs (DC) SCFL I/O levels fully compatible Differential or single ended I/Os Duty Cycle control Echo inputs available Power Consumption: 1.25W DM4134 Eye Diagram 5 GHz Clock Input 15

16 DM4122 2:1 Mux DM4122 Output data rate range: DC-12.5 Gb/s 900 mvpp typical single ended output dynamic Input sensitivity: single ended input > 300 mv 1.0ps jitter RMS Output Rise time (20%-80%): < 27 ps Output Fall time (20%-80%): < 24 ps Full SCFL input levels compatibility matched AC/DC coupled inputs matched AC/DC coupled clock input matched AC/DC coupled Selector input matched DC coupled output Power consumption: V), DM4122 Eye Diagram 12.5 Gb/s Data Output 16

17 DM4122A 2:1 Combinatorial Mux DM4122A Output data rate range: DC-12.5 Gb/s 900 mvpp typical single ended output dynamic Input sensitivity: single ended input > 300 mv 1.2ps jitter RMS Output Rise time (20%-80%): < 27 ps Output Fall time (20%-80%): < 24 ps Full SCFL input levels compatibility matched AC/DC coupled inputs matched AC/DC coupled Selector input matched DC coupled output up to 12.5 Gb/s AND/OR logic gate implementation up to 12.5 Gb/s NRZ to RZ converter up to 12.5 Gb/s input data rate static switch up to 12.5 Gb/s output data rate mux Power consumption: W DM4122A Eye Diagram 12.5 Gb/s NRZ Data Input (NRZ to RZ conversion application) 17

18 DM4080 Single chip clock divider by four Input clock rate range: DC-12.5 Gb/s 900 mvpp typical single ended output dynamic Input sensitivity: single ended input > 300 mv 1.2ps jitter RMS Output Rise time (20%-80%): < 27 ps Output Fall time (20%-80%): < 24 ps Full SCFL input levels compatibility matched AC/DC coupled inputs matched DC coupled output Power consumption: 1.3 W VEE Device Eval Board CLKD4 Not used CLK IN CLK IN\ CLKD2 CLKD4\ Eye Diagram 12.5 GHz clock Input 18

19 DM4120A GaAs HBT 4 to 1 combinatorial Mux VEE DC clips (4 access points) Southwest High Performance SMA connector DM4120A on a quick 16 mm package demo board A B C D Selectors DC clips (S0, S0b, S1, S1b) VEE = -5.0 V (176 ma) Bit Rate = 12.5Gbps 19

20 DM3022D GaAs HBT linear buffer DM3022 Buffer function 3-dB bandwidth: 10GHz Single-ended gain: 6 db Standard bias supply : -5V, +5V Power Consumption: 1.35W 1% total harmonic distortion at Pout: 0dBm Low group delay Low jitter CMRR: >20dB at 10GHz AC and DC input coupling (SCFL compatible) AC and DC output coupling 20

21 DM4006D InP HBT 13.0 DFF DM4006 Supports data rate up to 13 Gb/s Fast output rise time (20%-80%) < 22 ps Fast output fall time (20%-80%) < 20 ps 450 mvpp single ended output DC coupled data and clock input AC or DC coupled data output Differential or single ended inputs Low power consumption: 270 mw DM Gb/s PRBS data input Vin = +/-150 mvpp (Data and Clock) 12.5 Gb/s PRBS data input Vin = +/-150 mvpp (Data and Clock) Eye Diagram 12.5 Gb/s 21

22 DM4124 4:1 Mux InP HBT 13.0 Gbps DM4124 Supports data rate DC up to 13 Gb/s Fast output rise time (20%-80%) < 22 ps Fast output fall time (20%-80%) < 20 ps 450 mvpp single ended output DC coupled data and clock input AC or DC coupled data output Differential or single ended inputs Low power consumption: 350 mw Eye Diagram 12.5 Gb/s (dynamic test 2^31-1) Eye Diagram 2.5 Gb/s (dynamic test 2^31-1) 22

23 Contacts For any information please contact: or fax number : or land line phone number :

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