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1 EE 224: INTRODUCTION TO DIGITAL CIRCUITS & COMPUTER DESIGN Lecture 5: Sequential Logic - 2 Analysis of Clocked Sequential Systems 4/2/2 Avinash Kodi, kodi@ohio.edu Course Administration 2 Hw 2 due on today Monday 4/26 Hw 3 posted, due on Friday 4/3 by : PM (drop outside my office) Quiz 2 on Wednesday esday 4/28 Exam on Monday 5/3 syllabus next slide

2 Exam - Syllabus 3 Number System and Binary Arithmetic Boolean Algebra, Simplification and K-maps Combinational Logic (Adders, Muxes, Decoders, PLAs) Sequential Logic (Latches and Flip Flops) Analysis s of Clocked Sequential Logic (Moore and Mealy machines) FF Summary 4 Flip-Flop Characteristic Table JK Flip-Flop J K Q + Operation Q No Change Reset Set Q Complement D Flip-Flop D Q + Operation Reset Set SR Flip-Flop S R Q + Operation Q No Change Reset Set? Undefined T Flip-Flop T Q + Operation Q No Change Q Complement 2

3 FF Transition Input Codes 5 Using FF state tables we can derive the input conditions that will cause specific transitions in each FF output 4 possible transitions: D & T FFs have welldefined input conditions in each case J-K FF has Don t Care () conditions FF Outputs FF Inputs Q(t) Q(t+) T D J-K - - Key to follow sequential logic circuit design examples (i.e. counters) - - FF Excitation Table 6 Flip-Flop Excitation Table JK Flip-Flop Q Q + J K D Flip-Flop Q Q + D SR Flip-Flop Q Q + S R T Flip-Flop Q Q + T 3

4 7 Analysis by Signal Tracing and Timing Charts Analysis steps: Assume an initial iti state t of FFs (all FFs reset to unless specified) For the input sequence, determine the circuit output(s) and FF inputs Determine the new set of FF states after the next active clock edge Determine the output(s) that corresponds to the new states 8 Two Types of Clocked Sequential Circuits Moore Machine: If the output of a sequential circuit is a function of the present state only Mealy Machine: If the output of a sequential circuit is a function of both the present state and the input 4

5 State Tables and Graphs 9 State Table Construction Step : Determine the FF input equations and output t equations from the circuit Step 2: Derive the next state equation for each FF from input equations from the circuit D FF: Q + = D T FF: Q + = T Q SR FF: Q + = S + R Q JK FF: Q + = JQ + K Q Step 3: Plot a next state map for each FF Step 4: Combine the maps to form a state table Example of Moore s Machine (/4) A A B B CLK D A CLK D B = A B D A = B D B = + A 5

6 Example of Moore s Machine (2/4) Assume the initial value of A =, B =, = CLK A B ns 2ns 3ns 4ns 5ns 6ns 7ns 8ns 9ns ns Example of Moore s Machine (3/4) 2 Step : FF input equations and output equations: = A B D A = B D B = + A Step 2: Next state equations for the FF are: A + = B B + = + A Step 3: Corresponding K-maps for A + and B + 6

7 Example of Moore s Machine (4/4) 3 Step 4: Combine the K-maps into transition table shown here from which states can be derived A + B + = = Present State Next State = = Present Output () S S3 S S S S2 S2 S S2 S3 S2 S S S3 S2 S Example of Mealy Machine (/4) 4 A A B B K A J A K B J B CLK CLK B A A B B A A + = J A A + K A A = BA + A B + = J B B + K B B = B + (A) B = B + B + A B = A B + B + A 7

8 Example of Mealy Machine (2/4) 5 A B False Output False Output ns 2ns 3ns 4ns 5ns 6ns 7ns 8ns 9ns ns Example of Mealy Machine (3/4) 6 Step : FF input equations and output equations: J A = B, K A = J B =, K B = A Step 2: Next state equations for the FF are: A + = BA + A B + = B + B + A B = A B + B + A Step 3: Corresponding K-maps for A + B + and 8

9 Example of Mealy Machine (2/4) 7 Step 4: Combine the K-maps into transition table shown here from which states can be derived Present State Next State Present A + B + = = = = = = Output () = = S S S S S S2 S2 S2 S S3 S3 S / S / S / S3 / / S2 Design of a Sequence Detector (/3) 8 Circuit examines a string of s and s applied to input and generates an output = only when the prescribed sequence occurs with the assumption that can only change between clock cycles. Design the circuit so that the input sequence ending in will produce an output = coincident with the last. The circuit does not reset when a occurs. = = Is this a Mealy machine or Moore machine? 9

10 Design of a Sequence Detector (2/3) 9 Present State Next State Present = = Output () = = S / S S S S S2 S S2 / S / S2 S S A + B + = = = = Design of a Sequence Detector (3/3) 2 A + = B B + = = A

11 How about Moore Machine? 2 S / S3 / S / S2 / Present State Next State = = Present Output () S S S S S2 S S2 S S3 S3 S2 S A + B + = = Complex Design - 22 The output = if the input sequence ends in either or and should be otherwise. Here s a typical sequence = =

12 Solution - 23 S S / S4 / State S Sequence Ends In Reset / / S (but not ) S2 S2 / / S3 S3 S4 (but not ) / S5 S5 Complex Design A sequential circuit has one input () and two outputs ( and 2). An output = occurs every time when the input sequence is completed, provided that the sequence has never occurred. An output 2 = occurs every time the input sequence is completed. Note that once 2 = output has occurred, = can never occur but not vice versa. Find a mealy state graph and table. = = 2 = 2

13 Solution S / / / S7 S S3 / / / S2 / S4 S5 / / S6 Complex Design A sequential circuit has two inputs ( and 2) and one output. The output remembers the constant value unless one of the following input sequence occurs: The input sequence 2 =, causes the output to become The input sequence 2 =, causes the output to become The input sequence 2 =, causes the output to change value (toggle) 3

14 27 Solution 3 (see text for complete solution Previous Input Output () State Designation or S or S S2 S3 S4 S5 4

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