EEE2135 Digital Logic Design Chapter 6. Latches/Flip-Flops and Registers/Counters 서강대학교 전자공학과

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1 EEE235 Digital Logic Design Chapter 6. Latches/Flip-Flops and Registers/Counters 서강대학교 전자공학과

2 . Delay and Latches ) Signal Storage a. as voltage level static memory b. as charges dynamic memory 2) Delays a. due to gates and interconnection lines b. Uncertain delays : I. typical (nominal), min/max delays II. Statistical delay c. Rising/falling delay: % 9%, 9% % of voltage swing d. Transport delay : port- to-port (pin-to-pin) delay e. Inertial delay I. Tends to block narrow pulses (inertia, resistance tplh to tphl change) II. Energy to charge/discharge internal capacitances III. Unbalance between rising & falling delays

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4 Flip-flop Register. : noise(perfact signal.)

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7 3) Latches a. Closed signal path : feedback loop b. Stability and Meta-stability I. Unstable Leads to oscillation II. Meta-stable Temporarily stuck between and Responsible for rare and hard-to-find failure III. Bistable Two stable states A B

8 c. SR Latches i. Structure ii. Behavior R S S R n *X n S R n n *X Forbidden inputs in RS latch with NANDs/NORs Unpredictable behavior : depends on propagation delay of NORs/NANDs forbidden input conditions It is sensitive to noise To alleviate the noise problems, a control signal is used - Gated SR latch iii. Level-sensitive & Asynchronous hard to control

9 Improvement of SR-latch (Gated SR-latch) I. Controlled by a control signal II. Still level-sensitive (w.r.t. control signal) III. Short duty cycle to prevent errors d. Gated SR latch - It can be usable SR latch S Control R Still, problem with SR latch Noise-sensitivity and forbidden input conditions

10 4) Latch Applications a. as a temporary storage element needed for data processing and I/O circuits without complex feedback b. to reduce glitches c. RS latch has forbidden input condition - D latch

11 2. Clocks and Flip-flops ) Basic Concepts a. More reliable storage elements in more general sequential circuits b. F/F: a bistable memory with precise timing control (by clock) 2) Clocking Methods a. Level-sensitive : latches b. Positive (negative) edge-triggered * F/Fs use the clock edge for the output change

12 A negative edge-triggered SR flip-flop (a simple circuit) S R Clock

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14 A negative edge-triggered SR flip-flop (a simple circuit) S R Clock

15 3) A positive-edge-triggered D flip-flop P3. P = P2 = and P3 = D, p4 = D when Clock = 2. P = D P2 = D when Clock goes to high 3. Further changes in D do not affect when Clock = if D = at then P2 = -> P4 = regardless of D if D = at then P = -> P2 = P3 = regardless of D P3, P4 must be stable when Clock goes to high : Setup time is delay from D through gate 4 to gates and 3 2 P 5 Clock 3 P2 6 (n+) = D(n) D D(n) (n+) D 4 P4 Clock (a) Circuit (b) Graphical Symbol (c) Transition Table

16 Master-slave D flip-flop Both clocking edges Preset D Clock Clear (a) Circuit Reset(Clear) and Preset: Asynchronous inputs

17 4) JK Flip-flop a. Structure b. Transition Table - Next page J(n) K(n) (n+) (n) (n) c. Transition-map for (n+) d. Excitation table for deriving transition function J(n) K(n) (n) (n) (n+) J(n)K(n) S(n)R(n) D(n) x x x x x x

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19 JK flip-flop J K Clock D (a) Circuit (n+) = J(n)(n) + K(n)(n) : JK F/F (n+) = S(n)R(n) + R(n)(n) : SR F/F (n+) = D(n) : D F/F J K (b) Transition functions (c) Graphical symbol

20 T flip-flop T Clock D T Clock D

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22 3. Flip-flop Behavior ) States a. Internal state and total state (the set of stored data ) b. State transition table and diagram I. Defines a memory s(state Register) next state function II. Allows repetitive behavior to be easily visualized 2) State Behavior a. Flip-flop behavior described by means of state table/diagram b. Each transition is triggered by clock signal c. Described by characteristic equation JK flip-flop ( n ) J( n) ( n) K( n) ( n) (, ) (, ) (, ) (, ) (, ) Set (, ) Reset (, ) (, )

23 3) Registers a. A set of flip-flops with common control logic b. Parallel-load type, shift-type, shift with parallel-load c. A simple shift register In D D D D Out Clock (a) Circuit t t t 2 t 3 t 4 t 5 t 6 t 7 In = Out (b) A sample sequence

24 d. Parallel-load shift register Parallel output 3 2 D D D D Serial input Shift/Load Parallel input Clock

25 4) Counters a. Asynchronous (Ripple) Counter I. A cascade of flip-flops, each of which toggling its successor II. Slow, lack of generality in design process b. Synchronous Counter I. Popular II. Uses a common clock for all f/f s c. Ring Counter I. Rotates a single thru all its flip-flops II. State diagram III. Decoder is embedded d. Johnson Counter I. Similar to ring counter II. State diagram III. Only one bit change between adjacent states no glitches

26 Synchronous Counter Clock T T T 2 T 3 (a) Circuit Clock 2 3 Count (b) Timing diagram

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33 Ring Counter n D PR D D R R R Reset Clock

34 Johnson Counter n D D D R R R Reset Clock

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37 F/F Timing t SU t SU t h Clk t ff t CC D Inputs to f/f stabilized f/f outputs stabilized t P, clk > t SU + t ff + t CC + margin f clk < /(t SU + t ff + t CC + margin)

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39 4. Memory An SRAM cell Sel Data Data An DRAM cell Data Sel

40 A 2 m x n SRAM block Data inputs d n d n 2 d Write Sel Sel Address a a a m m -to-2 m decoder Sel 2 Sel 2 m Read Data outputs q n q n 2 q

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