Sequential Logic Circuits

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1 Sequential Logic Circuits By Dr. M. Hebaishy Digital Logic Design Ch-

2 Rem.!) Types of Logic Circuits Combinational Logic Memoryless Outputs determined by current values of inputs Sequential Logic Has memory Outputs determined by previous and current values of inputs inputs functional spec timing spec outputs Digital Logic Design Ch-2

3 Outlines Introduction Sequential Circuits Storage Elements: Latches Storage Elements: Flip Flops Analysis of Clocked Sequential Circuits State Reduction and Assignment Design Procedure Digital Logic Design Ch-3

4 Introduction Asynchronous Inputs Combinational Circuit Memory Elements Outputs Synchronous Inputs Combinational Circuit Outputs Clock Flip-flops Digital Logic Design Ch-4

5 Sequential Circuits There are two main types of sequential circuits : A synchronous sequential circuit is a system whose behavior can be defined from the knowledge of its signals at discrete instants of time. An asynchronous sequential circuit depends upon the input signals at any instant of time and the order in which the inputs change. The storage elements (memory) used in clocked sequential circuits are called flipflops. A flip-flop is a binary storage device capable of storing one bit of information. In a stable state, the output of a flip-flop is either or. A sequential circuit may use many flip-flops to store as many bits as necessary. Digital Logic Design Ch-5

6 Outputs of sequential logic depend on current and prior input values it has memory. Some definitions: State: all the information about a circuit necessary to explain its future behavior Latches and flip-flops: state elements that store one bit of state Sequential Circuits Give sequence to events Have memory (short-term) Use feedback from output to input to store information Digital Logic Design Ch-6

7 State Elements The state of a circuit influences its future behavior State elements store state Bistable circuit SR Latch SR Flip Flop D Flip Flop (Controlled Latch) J k Flip Flop Digital Logic Design Ch-7

8 Bistable Circuit Fundamental building block of other state elements Two outputs:, No inputs I2 I I I2 Digital Logic Design Ch-8

9 Bistable Circuit Analysis Consider the two possible cases: = : then =, = (consistent) I I2 = : then =, = (consistent) I I2 Stores bit of state in the state variable, (or ) But there are no inputs to control the state Digital Logic Design Ch-9

10 S R Latch SR Latch The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates, and two inputs labeled S for set and R for reset. SR latch with NOR gates Digital Logic Design Ch-

11 SR latch with NAND gates Digital Logic Design Ch-

12 SR Latch S R = R S Initial Value Digital Logic Design 2 Ch-2

13 Latches SR Latch S R = = R S Digital Logic Design 3 Ch-3

14 Latches SR Latch R S R = = S Digital Logic Design 4 Ch-4

15 SR Latch R S R = = = S Digital Logic Design 5 Ch-5

16 Latches SR Latch R S R = = = S Digital Logic Design 6 Ch-6

17 SR Latch R S R = = = = S Digital Logic Design 7 Ch-7

18 SR Latch R S R = = = = S Digital Logic Design 8 Ch-8

19 SR Latch R S S R = = = = = Digital Logic Design 9 Ch-9

20 SR Latch R S R No change Reset S = = Set Invalid S S R = = Invalid Set R Reset No change Digital Logic Design Ch-2

21 SR Latch SR stands for Set/Reset Latch Stores one bit of state () Control what value is being stored with S, R inputs Set: Make the output (S =, R =, = ) Reset: Make the output (S =, R =, = ) Must do something to avoid invalid state (when S = R = ) SR Latch Symbol R S Digital Logic Design Ch-2

22 S R Flip Flop S - R F F (Controlled Latch) R R S S C C S S R R C S R x x No change No change Reset Set = Invalid Digital Logic Design Ch-22

23 Draw the Time diagram for the output for Clocked S-R Flip Flop if the Pulses of Inputs (CK, S, R ) as shown below, Let the initial output =. Digital Logic Design Ch-23

D -Flip Flop D Type Flip Flop (D = Data) One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that inputs S and R are

24 D -Flip Flop D Type Flip Flop (D = Data) One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that inputs S and R are never equal to at the same time. This is done in the D latch, shown in Fig Symbol Modes of operation Flip Flop Circuit CK D x No change Reset Set Digital Logic Design Ch-24

25 Timing Diagram CK D t Output may change D Type Latch Time Diagram Digital Logic Design Ch-25

26 Latch VS Flip-Flops Controlled latches are level-triggered C Flip-Flops are edge-triggered CLK Positive Edge CLK Negative Edge Digital Logic Design Ch-26

27 Master-Slave D Flip-Flop D D C D Latch (Master) D C D Latch (Slave) CLK Master Slave CLK D Looks like it is negative edgetriggered Master Slave Digital Logic Design Ch-27

J-K Flip Flop J-K Flip Flop JK flip-flop has two inputs and performs all three operations. The circuit diagram of a JK flip-flop constructed as shown in Fig. gates is shown in Fig.

28 J-K Flip Flop J-K Flip Flop JK flip-flop has two inputs and performs all three operations. The circuit diagram of a JK flip-flop constructed as shown in Fig. gates is shown in Fig. The J input sets the flip-flop to, the K input resets it to, and when both inputs are enabled, the output is complemented (Toggle) Symbol Table Characteristics Circuit Diagram J Inputs K CK Output Mode No Change Reset Set Toggle Digital Logic Design Ch-28

29 Digital Logic Design Ch-29

30 T - Flip Flop T Flip-Flop T J D T K T (t+) T (t) (t) No change Toggle Digital Logic Design Ch-3

31 Flip-Flop Characteristic Tables D (t +) Reset Set (t+) = D J K (t +) (t) (t) No change Reset Set Toggle t + = J+ K T (t +) (t) (t) No change Toggle (t +) = T Digital Logic Design Ch-3

32 Analysis / Derivation J J K (t ) (t+) No change Reset Using K-Map to Minimize The table J J K K K K K Set After Minimization Toggle t + = J+ K Digital Logic Design Ch-32

33 Analysis of Clocked Sequential Circuits The Steps of Analysis are summarized into: Circuit diagram Equation State table State diagram The State State = Values of all Flip-Flops x D A Example Initial values: A B = D B CLK y Digital Logic Design Ch-33

34 State Equations A(t+) = D A = A(t) x(t)+b(t) x(t) = A x + B x x D A B(t+) = D B = A (t) x(t) = A x CLK D B y(t) = [A(t)+ B(t)] x (t) = (A + B) x y Digital Logic Design Ch-34

35 Analysis of Clocked Sequential Circuits State Table (Transition Table) Present State Input Next State Output A B x A B y x CLK A(t+) = A x + B x B(t+) = A x y(t) = (A + B) x D D A B y t t+ t Digital Logic Design 35 Ch-35

36 Analysis of Clocked Sequential Circuits State Table (Transition Table) Present State Next State Output x = x = x = x = A B A B A B y y x CLK D D A B y t t+ t A(t+) = A x + B x B(t+) = A x y(t) = (A + B) x Digital Logic Design 36 Ch-36

37 Analysis of Clocked Sequential Circuits State Diagram AB input/output / / / / / / / / Present State x Next State CLK D D Output x = x = x = x = A B A B A B y y Digital Logic Design Ch-37 A B y

38 D Flip-Flops Example: Present State Input Next State A x y A x y CLK D A(t+) = D A = A x y,,,, A Digital Logic Design Ch-38

39 JK Flip-Flops J A Example : x K Present State I/P Next State Flip-Flop Inputs J B A B x A B J A K A J B K B CLK J A = B K A = B x J B = x K B = A x A(t+) = J A A + K A A = A B + AB + Ax B(t+) = J B B + K B B = B x + ABx + A Bx K Digital Logic Design Ch-39

40 JK Flip-Flops J A Example: x K Present I/P Next Flip-Flop State State Inputs A B x A B J A K A J B K B J K B CLK Digital Logic Design Ch-4

41 T Flip-Flops Example: x T R A y Present I/P Next F.F State State Inputs O/P A B x A B T A T B y CLK T A = B x T B = x y = A B A(t+) = T A A + T A A = AB + Ax + A Bx B(t+) = T B B + T B B = x B T R Reset B Digital Logic Design Ch-4

42 T Flip-Flops x T A y Example: R Present I/P Next F.F State State Inputs O/P A B x A B T A T B y / / / T B R CLK Reset / / / / / Digital Logic Design Ch-42

43 Mealy and Moore Models The Mealy model: the outputs are functions of both the present state and inputs. The outputs may change if the inputs change during the clock pulse period.» The outputs may have momentary false values unless the inputs are synchronized with the clocks. The Moore model: the outputs are functions of the present state only. The outputs are synchronous with the clocks. Digital Logic Design Ch-43

44 Mealy Present I/P Next State State O/P A B x A B y Moore Present I/P Next State State O/P A B x A B y For the same state, the output changes with the input For the same state, the output does not change with the input Digital Logic Design Ch-44

45 Moore State Diagram State / Output / / / / Digital Logic Design Ch-45

46 State Reduction and Assignment State Reduction Reductions on the number of flip-flops and the number of gates. A reduction in the number of states may result in a reduction in the number of flip-flops. An example state diagram showing in Fig. Digital Logic Design Ch-46

47 State: a a b c d e f f g f g a Input: Output: Only the input-output sequences are important. Two circuits are equivalent» Have identical outputs for all input sequences;» The number of states is not important. Digital Logic Design Ch-47

48 Equivalent states Two states are said to be equivalent» For each member of the set of inputs, they give exactly the same output and send the circuit to the same state or to an equivalent state.» One of them can be removed. Digital Logic Design Ch-48

49 Reducing the state table e = g (remove g); d = f (remove f); Digital Logic Design Ch-49

50 The reduced finite state machine State: a a b c d e d d e d e a Input: Output: Digital Logic Design Ch-5

51 The checking of each pair of states for possible equivalence can be done systematically using Implication Table. The unused states are treated as don't-care condition fewer combinational gates. Reduced State diagram Digital Logic Design Ch-5

52 Design Procedure Design Procedure for sequential circuit The word description of the circuit behavior to get a state diagram; State reduction if necessary; Assign binary values to the states; Obtain the binary-coded state table; Choose the type of flip-flops; Derive the simplified flip-flop input equations and output equations; Draw the logic diagram; Digital Logic Design Ch-52

53 Design of Clocked Sequential Circuits with D F.F. Example.: Detect 3 or more consecutive s Synthesis using D Flip-Flops D A (A, B, x) = (3, 5, 7) = A x + B x D B (A, B, x) = (, 5, 7) = A x + B x y (A, B, x) = (6, 7) = A B B A x B A x B A x Digital Logic Design Ch-53

54 Example: Detect 3 or more consecutive s Synthesis using D Flip-Flops D A = A x + B x x D A D B = A x + B x y = A B y D B CLK Digital Logic Design Ch-54

55 uiz -The D latch constructed with four NAND gates and an inverter. Consider the following three other ways for obtaining a D latch. In each case, draw the logic diagram and verify the circuit operation. (a) Use NOR gates for the SR latch part and AND gates for the other two. An inverter may be needed. (b) Use NOR gates for all four gates. Inverters may be needed. (c) Use four NAND gates only (without an inverter). This can be done by connecting the output of the upper gate (the gate that goes to the SR latch) to the input of the lower gate (instead of the inverter output). 2- Construct a JK flip-flop, Show that the characteristic equation for the complement output of a JK flip-flop is (t + ) = J + K 3- A PN flip-flop has four operations: clear to, no change, complement, and set to, when inputs P and N are,,, and, respectively. (a) Tabulate the characteristic table. (b) * Derive the characteristic equation. (c) Show how the PN flip-flop can be converted to a D flip-flop 4- A sequential circuit with two D flip-flops A and B, two inputs, x and y ; and one output z is specified by the following next-state and output equations A(t + ) = xy + xb B(t + ) = xa + xb z = A (a) Draw the logic diagram of the circuit. (b) List the state table for the sequential circuit. (c) Draw the corresponding state diagram. Digital Logic Design Ch-55

56 Sol: A B C Digital Logic Design Ch-56

57 Sol : 2 Digital Logic Design Ch-57

58 Ans(3) (C) Digital Logic Design Ch-58

59 Sol. 4 Digital Logic Design Ch-59

60 Digital Logic Design Ch-6

61 5- A sequential circuit has one flip-flop, two inputs x and y, and one output S. It consists of a full-adder circuit connected to a D flip-flop, as shown in Fig. Derive the state table and state diagram of the sequential circuit. Digital Logic Design Ch-6

62 Digital Logic Design Ch-62

63 6- A sequential circuit has two JK flip-flops A and B and one input x The circuit is described by the following flip-flop input equations : J A = x K A = B J B = x K B = A a) Derive the equations A(t+) and B(t+) by substituting the input equations for the J and K variables. b) Draw the state diagram of the circuit. Sol: Digital Logic Design Ch-63

64 7- A sequential circuit has two JK flip-flops A and B, two inputs x and y, and one output z. The flip flop input equations and circuit output equation are : J A = Bx + B y K A = B x y J B = Ax K B = A + x y z = Ax y + Bx y a) Draw the logic diagram of the circuit. b) Tabulate the state table c) Derive the state equations for A and B. Digital Logic Design Ch-64

65 Digital Logic Design Ch-65

66 Digital Logic Design Ch-66

67 8- Design a sequential circuit with two D flip flops A and B, and one input x_in. a)when x_in =, the state of the circuit remains the same. When x_in =, the circuit goes through the state transitions from to, to, to, back to and repeat. b) When x_in =, the state of the circuit remains the same. When x_in=, the circuit goes through the state transition from to, to, to back to, and repeats Digital Logic Design Ch-67

68 Digital Logic Design Ch-68

69 9- List State table for the JK flip-flop using as the present and next state and J and K as inputs. Design the sequential circuit specified by the state table using D- Flip Flop. Sol. Digital Logic Design Ch-69

70 END Digital Logic Design Ch-7

Digital Logic Design I

Digital Logic Design I Synchronous Sequential Logic Mustafa Kemal Uyguroğlu Sequential Circuits Asynchronous Inputs Combinational Circuit Memory Elements Outputs Synchronous Inputs Combinational Circuit