White Paper Versatile Digital QAM Modulator

Transcription

1 White Paper Versatile Digital QAM Modulator Introduction With the advancement of digital entertainment and broadband technology, there are various ways to send digital information to end users such as cable and satellite subscribers. The current digital cable systems deployed around the world use the Quadrature Amplitude Modulation (QAM) standard, which defines the input data framing structure, channel forward error encoding, filtering, and QAM mapping. With digital TV, the typical downstream signal uses either a 64- or 256-QAM scheme. The data source is either ATM packets or MPEG2 transport packets (used for digital TV applications). The differences in the QAM standards are in the error coding section, which is broken down by Annex A, B, or C. The North American standard uses Annex B for encoding. The Stratix II FPGA logic structure combined with enhanced DSP blocks offers a flexible way to implement the key elements of the QAM signal processing path in any region. Table 1 lists the different digital cable standards deployed in key areas of the world. Table 1. Digital Cable Standards Location QAM Standard Annex North America ITU-T/J.83B B Europe DVB-C A China DVB-C, DTV-C A Japan ITU-T/J.83B C QAM Modulator Application Requirements Because manufacturers market and adapt their products to different geographical locations that have different standards, it is impractical to use application-specific standard product (ASSP) semiconductors or custom ASICs to design a cable system. The Stratix II FPGA can help design a system that can adapt to a wide variety of standards within digital TV standards. Designers can implement all the baseband signal processing in the Stratix II FPGA, and can configure the FPGA while cable systems are operating. Multiple QAM encoder channels can also be implemented with a single FPGA to provide the flexibility of hardware upgrades and cost savings. Figure 1 shows the major blocks of a typical one-channel QAM modulator. Figure 1. One-Channel QAM Modulator WP-STXIIQAM-1.1 January 2006, ver

2 Versatile Digital QAM Modulator Altera Corporation Data Source The data input format for a digital TV modulator is either a parallel or a serial MPEG2 transport interface. Most head-end equipment uses the DVB-ASI serial interface. The Stratix II device's dedicated LVDS I/O pins, capable of up to 1-Gigabits per second (Gbps) performance, are ideal for the multiple DVB-ASI channel inputs implementation. Different video streams can be multiplexed onto the FPGA QAM modulator design for transmission. In Annex A/C, the MPEG2 transport stream is synchronized with a synchronized byte of 0x07 hex. The synchronized data is then scrambled per DVB/DAVIC standards. In Annex B, the input logic searches the MPEG2 transport stream for the synchronized byte and then replaces it with a checksum byte to improve error detection capability. Handling the data stream requires a lot of common logic functions. The Stratix II family's new logic structure goes beyond the simple, fixed-size four-input LUT structure and extends its logic capacity to efficiently construct any logical functions with five or six inputs in one entity. A Stratix II adaptive logic module (ALM) can also implement many seven-input functions. By supporting logical functions with more than four variables per ALM, the Stratix II logic structure increases the performance of a design by: Reducing the number of logic levels required for the overall combinational logic. Reducing the extra programmable routing needed in the simple, fixed-size four-input LUT implementation. Reducing the stress on the demand for general routing resources. Research has shown that wider LUTs provide better performance, while narrower LUTs provide better logic efficiency. Stratix II ALMs offer not only the desired performance, but also adaptively accommodate the logic functions with different numbers of inputs to provide exceptional logic efficiency that is 25% better than prior FPGAs. The Stratix II ALMs can effectively reduce the logic resource requirements of a design by: Optimally creating functions with larger input counts and packing those with functions with smaller input counts (for example, in Stratix II devices, a five-input and a three-input function can be placed together in one ALM). Reducing the need for logic duplication by sharing logic resources for different combinational logic with common inputs. Implementing complex arithmetic functions and combining logic and arithmetic operations such as data selection before summation and subtraction. Implementing high-input-count arithmetic functions such as an adder tree. Allowing register packing. Using a register chain. Memory & Multiplexer for Channel Encoding To improve the performance of a communication channel, Forward Error Correction (FEC) channel coding corrects errors during transmission. The FEC acts as an overhead to the actual data payload. The most common FEC is Reed-Solomon encoding, which calculates the checksum appended to the data packet at the source. At the receiving end of the transmission, any discrepancy in the checksum indicates an error in transmission. Reed-Solomon corrects for block errors, which are typically caused by burst errors across the transmission channel. Furthermore, words in error can be corrected up to one correction for every two checksum words. The Reed-Solomon encoder is already a proven Altera MegaCore function. The ITU J.83 Annex B FEC has an additional powerful channel coding scheme called trellis coding. Because trellis coding is embedded in the modulation process, it often carries the name trellis coded modulation (TCM). See the Trellis Coded Modulation section for more information. Interleaving Data interleaving spreads data over a variable period of time in order to combat adjacent burst errors that the Reed-Solomon decoder cannot handle. Without data interleaving, many adjacent errors cannot be corrected. With 2

3 Altera Corporation Versatile Digital QAM Modulator data interleaving, data is transmitted by spacing the content of consecutive packets. Therefore, burst errors are distributed over many data packets, so that the FEC has fewer errors to correct in each packet. Data interleaving transmits the first word of the current packet, then the first word of the previous packet, then the first word of the second previous packet, and so on, until all first words of all packets are transmitted. It then starts again with the second words of the set of packets, and then the third words, and so on, until all the data is transmitted. Data interleaving requires many memory and multiplexing operations. The Stratix II device's logic structure is ideal for building multiplexer and demultiplexer structures, and can efficiently implement large multiplexers, barrel shifters, crossbar switches, and state machines. The Stratix II devices offer up to 9 Mbits of dedicated memory blocks that can be used for data interleaving. If required, external memory interfaces are also available for deeper interleaving. Stratix II FPGAs are available in advanced pin packages that provide board area savings as well as high pin-counts. For example, the Stratix II family is offered in the 1,508-pin FineLine BGA package with up to 1,150 user I/O pins. These high pin count packages offer easy access to I/O pins for implementing with external memory chips and other support devices in the system. Interleaving is defined by two parameters, I and J. I x J = packet size or multiples of packet size. A typical interleaver is shown in Figure 2. Figure 2. Interleaver Block Diagram In Annex B, the packet size is 128 words (122 data words and 6 RS checksum words), so the available interleaves are I = 128 x J = 1, or I = 64 x J = 2, or I = 32 x J = 4. Or the enhanced interleaves are I = 128 x J = 2, or I = 128 x J = 3, up to I = 128 x J = 8. In I =128 x J = 1, there is a set of 128 packets. In I = 128 x J = n, there are "n" sets of 128 packets. In I = m x J = n, there are "n"sets of "m" packets such that m x n = 128. Figure 3 shows the block diagram of an Annex B channel encoder. The interleaver depth can be 8, 12, 16, 32, 64, or 128 for DOCSIS, or 12 for EuroDOCSIS. The default value is 8 for DOCSIS. 3

4 Versatile Digital QAM Modulator Altera Corporation Figure 3. ITU J.83 Annex B Channel Encoder In Annex A / C, packet sizes are 204 words, and the interleaving is fixed at I = 12 x J = 17. Figure 4 shows the block diagram of an Annex A/C channel encoder. Figure 4. ITU J.83 Annex A/C Channel Encoder Trellis Coded Modulation Trellis Coded Modulation (TCM) is an encoder that selects an optimal sequence from the data stream and a map of the QAM constellation. The constellation in TCM is usually larger than required for the data stream, and the encoder generates a sequence of wider words mapped such that the transition distances in the constellation are maximized. Figure 5 shows the generic block diagram for a typical TCM. Figure 5. TCM Block Diagram The purpose of increasing the constellation size is to implement coding rules where transitions from a constellation point are allowed to go to only some specific other points (not all combinations are allowed), depending on the 4

5 Altera Corporation Versatile Digital QAM Modulator previous data. The objective is to increase the distance of transitions over that data-stream sequence. TCM reduces the probability of error for a given signal-to-noise ratio (SNR). Therefore, for a given error rate, the SNR can be reduced by "x" db, known as the coding gain. The TCM coding gain for the ITU J.83 Annex B is around 4.5 for 64QAM and 256QAM. The TCM block includes the differential encoder, binary convolutional encoder, and QAM mapper. Figures 6 and 7 show the mappings for a 64 and 256 QAM constellation diagram, respectively. Figure QAM Constellation Q Amplitude I Amplitude Possible Combinations of I & Q Figure QAM Constellation Q Amplitude I Amplitude Possible Combinations ofi&q Designers can use the Stratix II DSP blocks to implement a binary convolutional coder. The structure of a convolutional coder is similar to a digital filter. Figure 8 shows the convolutional encoder block diagram. 5

6 Versatile Digital QAM Modulator Altera Corporation Figure 8. Binary Convolutional Encoder Raised Cosine Filter Transmitting video data over a band-limited channel requires a filter to shape the digital pulses so that inter-symbol interference (ISI) can be controlled or eliminated. Typically, a programmable square-root raised cosine filter (a finite impulse response (FIR) filter) is used for pulse shaping in a cable transmission facility. Its transfer function is shown below. Ht () sin πt cos απt T = πt αt T T 2 The excess bandwidth factor's alpha value is either 12, 15, or 18 percent, depending on the standard used. The Stratix II device's enhanced DSP blocks can be used to efficiently implement a programmable filter for cable modulation. Table 2 compares the improvements for a 128-tap FIR decimating filter when using Altera's FIR Compiler 3.0. The design's digital filter must meet the following design specifications: 16-bit data and coefficients 80 db out of band rejection Pipeline = 1 Number of channels = 4 Parallel architecture Table 2. FIR Benchmark Comparison Between Stratix & Stratix II Devices Parameter Stratix Stratix II Adder tree type Binary Ternary Number of adders Logic elements (1) 3, Memory usage (M512) Speed (f MAX ) 248 MHz MHz Notes: 6

7 Altera Corporation Versatile Digital QAM Modulator (1) Logic elements for Stratix II devices refer to the ALUTs reported in the Quartus II software. (2) These numbers are preliminary. A key element of a digital filter is the adder. The Stratix II ALM offers a performance advantage in adder tree implementation by supporting the summation of three numbers in one step. Because of the ternary adder capability within Stratix II devices, the overall number of adders are reduced, leading to an 18% reduction in the logic resource usage compared to a Stratix device. The performance of a Stratix II device is increased by 22% over a Stratix device. The filter design equates to 35.1 GMACs (over 12x the capability of the fastest DSP processors available) and uses less than 3% of an EP2S180's logic resources (4683/ equivalent logic elements). Figure 9 shows a simple three-input adder in a Stratix and Stratix II device. Figure 9. Stratix Versus Stratix II Three-Input Adder Implementation When a three-input add operation is implemented in Stratix devices or any FPGA device that supports only two-input add operations in its logic structure, the sum is generated by repeatedly adding two numbers per operation each time. The performance of this binary-tree style summation is limited by the delay of each add stage as well as the delay of the programmable routing between each add stage. The ternary adder support (in shared arithmetic mode) in Stratix II ALMs collapses the two add stages into one and improves the performance by eliminating one add stage and the extra programmable routing. Digital Upconverter A numerically controlled oscillator (NCO) is a logic block that outputs a digital frequency based on a numerical input. The output waveform can be any type of waveform, but is typically a sawtooth (ramp), sine, or both sine and cosine. The output frequency is limited to one half of the master clock frequency. An NCO is composed of a programmable counter and a waveform lookup table. The counter, or phase accumulator, counts based on the frequency input. This frequency input is added to the value of the current count on each clock edge. The higher the input value, the faster the counter reaches its maximum value and rolls over. The counter value is used as the index to a look-up table (LUT). The LUT output determines the waveform output. One way to digitally upconvert a baseband real signal into a complex signal is to use a LUT function to create sine (in phase) and cosine (90 degree phase) multipliers. Altera's NCO compiler can create high-precision sinusoidal waveforms for this digital upconverter. Therefore, designers can use Stratix II DSP blocks, together with the built-in 7

8 Versatile Digital QAM Modulator Altera Corporation TriMatrix memory blocks, to implement an intermediate frequency (IF) upconverter with sample rates in excess of 300 Mbps. Due to the stringent requirements of modulation systems, NCOs must generate high-quality signals as measured by Spurious Free Dynamic Range (SFDR). A typical SFDR requirement for 3G is greater than 110 db. Implement this block with Altera's NCO Compiler using the following parameters: Phase accumulator precision 32 bits Angular precision 18 bits Magnitude precision 18 bits Algorithm: Multiplier based Dithering ON Table 3. NCO Benchmark Comparison Between Stratix & Stratix II Devices Parameters Stratix Stratix II Logic elements (1) Memory usage (M4K) 6 6 DSP block 9-bit elements 8 8 Maximum frequency (MHz) 279 MHz MHz Note: (1) The benchmark results are based on the prereleased Quartus II software and prereleased FIR filter core. The results may be different from the actual commercial release of the Quartus II software. (2) These numbers are preliminary. Conclusion A cable QAM modulator is signal processing intensive. With the Stratix II device's innovative logic structure, enhanced dedicated DSP blocks, and the revolutionary TriMatrix memory blocks, Stratix II devices are a perfect solution for cable head-end system designers who want flexibility and speedy time to market. In additional to the advanced features that Stratix II devices offer, Altera also provides an excellent set of IP cores and EDA tools to help simplify the design process. 101 Innovation Drive San Jose, CA (408) Copyright 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 8