Digital Circuit And Logic Design I. Lecture 8

Transcription

1 Digital Circuit And Logic Design I Lecture 8

2 Outline Sequential Logic Design Principles (1) 1. Introduction 2. Latch and Flip-flops 3. Clocked Synchronous State-Machine Analysis Panupong Sornkhom, 2005/2 2

3 Sequential Logic Design Principles (1)

4 1. Introduction Logic circuits are classified into two types Combinational logic circuit Outputs depend only on its current inputs Sequential logic circuit Outputs depend not only on its current inputs, but also on the past sequence of inputs, possibly arbitrarily far back in time. So it is inconvenient to describe the behavior of a sequential circuit by means of a table that lists outputs as a function of input sequence that has been received up until the current time. To know where you are going next, you need to know where you are now. More information, the current state is needed. Panupong Sornkhom, 2005/2 4

5 1. Introduction (cont.) The state of a sequential circuit is a collection of state variables whose values at any one time contain all the information about the past necessary to account for the circuit s future behavior. In TV channel-selector, the current channel number is the current state. Inside the TV, this state might be stored as seven binary state variables representing a decimal number between 0 and 127. Given the current state (channel number), we can always predict the next state as a function of the inputs In a digital logic circuit, state variables are binary values, corresponding to certain logic signals in the circuit. A circuit with n binary state variables has 2 n possible states. Sequential circuits are sometimes called finite-state machines. Panupong Sornkhom, 2005/2 5

6 1. Introduction (cont.) The state changes of most sequential circuits occur at times specified by a free-running clock signal. By convention, a clock signal is active high if state changes occur at the clock s rising edge or when the clock is HIGH, and active low in the complementary case. The clock period is the time between successive transitions in the same direction, and the clock frequency is the reciprocal of the period. The first edge or pulse in a clock period or some times the period itself is called a clock tick. The duty cycle is the percentage of time that the clock signal at its asserted level. Panupong Sornkhom, 2005/2 6

7 1. Introduction (cont.) Clock signal: (a) active high; (b) active low Panupong Sornkhom, 2005/2 7

8 2. Latches and Flip-Flops Flip-flop is a sequential device that normally samples its inputs and changes its outputs only at times determined by a clocking signal. On the other hand, latch is a sequential device that watches all of its inputs continuously and changes its outputs at any time, independent of a clocking signal. Panupong Sornkhom, 2005/2 8

9 2. Latches and Flip-Flops (cont.) S-R Latch An S-R (set-reset) latch based on NOR gates. The circuit has two inputs, S and R, and two outputs, labeled Q and QN, where QN is normally the complement of Q. S-R latch: (a) Circuit design using NOR gates; (b) function table Panupong Sornkhom, 2005/2 9

10 2. Latches and Flip-Flops (cont.) Typical operation of an S-R latch: (a) normal inputs; (b) S and R asserted simultaneously Logic symbol for an S-R latch: (a) without bubble; (b) preferred for bubble-to bubble logic design; (c) incorrect because of double negation Panupong Sornkhom, 2005/2 10

11 2. Latches and Flip-Flops (cont.) An S R latch with active-low set and reset inputs may be built from NAND gates S-bar-R-bar latch: (a) circuit design using NAND gates; (b) function table; (c) logic symbol Panupong Sornkhom, 2005/2 11

12 2. Latches and Flip-Flops (cont.) S-R Latch with Enable An S-R or S R latch is sensitive to its S and R inputs at all times. However, it may easily be modified to create a device that is sensitive to these inputs only when an enabling input C is asserted. S-R latch with enable: (a) circuit design using NAND gates; (b) function table; (c) logic symbol Panupong Sornkhom, 2005/2 12

13 2. Latches and Flip-Flops (cont.) D Latch S-R latches are useful in control applications, where we often think in terms of setting a flag in response to some condition and resetting it when conditions change. However, we often need latches simply to store bits of information. A D latch may be used in such an application. D latch: (a) circuit design using NAND gates; (b) function table; (c) logic symbol Panupong Sornkhom, 2005/2 13

14 2. Latches and Flip-Flops (cont.) Functional behavior of a D latch for various inputs Panupong Sornkhom, 2005/2 14

15 2. Latches and Flip-Flops (cont.) Edge-Triggered D Flip-Flop A positive-edge-triggered D flip-flop combines a pair of D latches to create a circuit that samples its D input and changes its outputs only at the rising edge of a controlling CLK signal. The triangle on the D flip-flop s CLK input indicates edge-triggered behavior and is called a dynamic-input indicator. Positive-edge-triggered D flip-flop: (a) circuit design using D latch; (b) function table; (c) logic symbol Panupong Sornkhom, 2005/2 15

16 2. Latches and Flip-Flops (cont.) Functional behavior of a positive-edge-triggered D flip-flop Panupong Sornkhom, 2005/2 16

17 2. Latches and Flip-Flops (cont.) Edge-Triggered D Flip-Flop (cont.) A negative-edge-triggered D flip-flop simply inverts the clock input, so that all the action take place on the falling edge of CLK_L; by convention, a falling-edge trigger is considered to be active low. Negative-edge-triggered D flip-flop: (a) circuit design using D latch; (b) function table; (c) logic symbol Panupong Sornkhom, 2005/2 17

18 2. Latches and Flip-Flops (cont.) Edge-Triggered D Flip-Flop (cont.) Some D flip-flops have asynchronous inputs that may be used to force the flip-flop to a particular state independent of the CLK and D inputs. These inputs, typically labeled PR (present) and CLR (clear), behave like the set and reset inputs on an SR latch. Positive-edgetriggered D flipflop with preset and clear: (a) logic symbol; (b) circuit design using NAND gates Panupong Sornkhom, 2005/2 18

19 2. Latches and Flip-Flops (cont.) Commercial circuit for a positive-edgetriggered D flipflop such as 74LS74 Panupong Sornkhom, 2005/2 19

20 2. Latches and Flip-Flops (cont.) Edge-Triggered D Flip-Flop with Enable A commonly desired function in D flip-flops is the ability to hold the last value stored, rather tan load a new value, at the clock edge. This is accomplished by adding an enable input, called EN or CE (clock enable). Positive-edge-triggered D flip-flop with enable: (a) circuit design; (b) function table; (c) logic symbol Panupong Sornkhom, 2005/2 20

21 2. Latches and Flip-Flops (cont.) Edge-Triggered J-K Flip-Flop. Edge-triggered J-K flip-flop: (a) equivalent function using edge-triggered D flip-flop; (b) function table; (c) logic symbol Panupong Sornkhom, 2005/2 21

22 2. Latches and Flip-Flops (cont.) Functional behavior of a positive-edge-triggered J-K flip-flop Panupong Sornkhom, 2005/2 22

23 2. Latches and Flip-Flops (cont.) Edge-Triggered T Flip-Flop. A T (toggle) changes state on every tick of the clock Positive-edge-triggered T flip-flop: (a) logic symbol; (b) function behavior Possible circuit designs for a T flip-flop: (a) using D flip-flop; (b) using J-K flip-flop Panupong Sornkhom, 2005/2 23

24 3. Clock Synchronous State-Machine Analysis State-Machine Structure Next state = F(current state,input) Output = G(current state,input) Clock synchronous state-machine structure (Mealy machine) Panupong Sornkhom, 2005/2 24

25 3. Clock Synchronous State-Machine Analysis State-Machine Structure A sequential circuit whose outputs depend on both state and input is called a Mearly machine In some sequential circuit, the outputs depend on the current state alone Output = G(current state) Such a circuit is called Moore machine Clock synchronous state-machine structure (Moore machine) Panupong Sornkhom, 2005/2 25

26 3. Clock Synchronous State-Machine Analysis Characteristic Equations The functional behavior of a latch of flip-flop can be described formally by a characteristic equation that specifies the flip-flop s next state as a function of its current state and inputs. By convention, the * suffix in Q* means the next value of Q. Notice that the characteristic equation does not describe detailed timing behavior of the device (latching vs. edge-triggered, etc.) Panupong Sornkhom, 2005/2 26

27 3. Clock Synchronous State-Machine Analysis Analysis of State Machines with D Flip-Flops The analysis of a clocked synchronous state machine has three basic steps: Determine the next-state and output functions F and G. Use F and G to construct a state/output table that completely specifies the next state and output of the circuit for every possible combination of current state and input (Optional) Draw a state diagram that presents the information from the previous step in graphical form. Panupong Sornkhom, 2005/2 27

28 3. Clock Synchronous State-Machine Analysis Panupong Sornkhom, 2005/2 28

29 3. Clock Synchronous State-Machine Analysis Logic equations that express the excitation signals as functions of the current state and input are called excitation equations and can be derived from the circuit diagram: Using the characteristic equation of D flip-flops, Q* = D, we can describe the next-state function of the example machine with equations for the next value of a state variables: These equtions, which express the next value of the state variables as a function of current state and input, are called transition equations Panupong Sornkhom, 2005/2 29

30 3. Clock Synchronous State-Machine Analysis Transition, state, and state/output tables for the state machine in preceding figure Panupong Sornkhom, 2005/2 30

31 3. Clock Synchronous State-Machine Analysis Once a state table is produced, we have only the output logic of the machine left to analyze. In the example machine, there is only a single output signal and it is a function of both current state and input (this is a mealy machine). So we can write a single output equation: Panupong Sornkhom, 2005/2 31

32 3. Clock Synchronous State-Machine Analysis State/output tables for Moore machines are slightly simpler. Suppose we removed the EN signal from the AND gate that produces the MAX output, producing a Moore-type output MAXS. Panupong Sornkhom, 2005/2 32

33 3. Clock Synchronous State-Machine Analysis (cont.) Analysis of State Machines with J-K Flip-Flops Clocked synchronous state machines built from J-K flip-flops can also be analyzed by the basic procedure in the preceding subsection. The only difference is that there are two excitation equations for each flip-flop one for J and the other for K. To obtain the transition equations, both of these but be substituted into the J-K s characteristic equation, Panupong Sornkhom, 2005/2 33

34 3. Clock Synchronous State-Machine Analysis (cont.) From the logic diagram, we can derive the following excitation equations: Panupong Sornkhom, 2005/2 34

35 3. Clock Synchronous State-Machine Analysis (cont.) Substituting into the characteristic equation for the J-K flip-flops, we obtain the transition equations: Reading the logic diagram, we can write the output equation Transition/output and state/output table Panupong Sornkhom, 2005/2 35

36 3. Clock Synchronous State-Machine Analysis (cont.) From the table, we can draw a state diagram: Panupong Sornkhom, 2005/2 36