BISHOP ANSTEY HIGH SCHOOL & TRINITY COLLEGE EAST SIXTH FORM CXC CAPE PHYSICS, UNIT 2 Ms. S. S. CALBIO NOTES lesson #39

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1 BISHOP ANSTEY HIGH SCHOOL & TRINITY COLLEGE EAST SIXTH FORM CXC CAPE PHYSICS, UNIT 2 Ms. S. S. CALBIO NOTES lesson #39 Objectives: Students should be able to Thursday 21 st January 10:45 am Module describe the operation of the triggered bistable; Module combine triggered bistables (T flip-flops) to make a 3-bit binary counter; T-TYPE BISTABLE T-type bistables, also called triggered or toggling flip-flops, are the building blocks of binary counters. They are modified RS bistables with extra components that enable successive pulses, applied to an input called the trigger T, to make it switch to and fro (or toggle ) from one stable state (e.g. Q = 0 and Q = 1) to the other ( Q = 1 and Q = 0). If the T input is high, the T flip-flop changes state (toggles) when the clock input changes. If the T input is low, the T flip-flop holds its previous value. T Q (current state) Qnext (next state) hold state hold state toggle toggle The S-R flip-flop may be modified in such a way that successive pulses to a single input called the trigger cause the flip-flop to switch from one stable state to the other. The circuit can be designed to trigger the bistable to change state with a pulse going down (from, say 6V to 0V) or up (from, say 0V to 6V). The output changes state at a specified point on a triggering input called the clock. The T-type flip-flop changes state either at the negative edge (falling edge) or at the positive edge (rising edge) of the clock signal. Clock signal Positive edges Negative edges The output of Q and NOT Q will not change (despite making changes to the inputs) in a clocked flipflop until receiving a signal from the clock.

2 To test a T-type bistable a debounced switch is usually needed: an ordinary switch normally bounces and makes contact more than once whereas the debounced switch when pressed and released gives only one pulse. The timing diagram in Figure 29 shows how the output Q switches state each time the voltage goes down from 6V to 0V i.e. on the downward edge of the pulse. If a series of pulses, known as a clock input, is applied to the trigger the output Q stays on logic 0 or stays on logic 1 for twice as long as the clock pulse. In effect the bistable divides the input frequency by two. This feature is used in timing devices such as digital watches and also in the binary counter which is explained below.

3 THE BINARY COUNTER Figure 30 shows the construction of a binary counter counting from 0 to the equivalent of decimal 7. Since it goes through eight output states before resetting to zero, it is known as a modulo-8 counter. Before the first pulse enters the counter is at The downward edge of the first pulse will cause Q1 to flip to 1 but the other two flip-flops will not be affected. So the output will change to (See timing diagram (Fig. 31) and note that Q3 is the most significant bit (m.s.b.) and Q1 the l.s.b., the units, so to read the number the order is reversed.) When the second pulse is received Q1 switches to 0. This sends a downward signal to the second bistable which switches output state so that Q2 is 1. Thus after two pulses the outputs are displaying which I equivalent to decimal 2. The third bistable does not receive a downward signal until Q2 switches off after the fourth pulse and so Q3 stays set on logic 0 twice as long as Q2 and four times as long as Q1. This principle of dividing the frequency by two may also be seen in the pattern of the binary numbers in the table below.

4 The 3-bit binary counter When several flip-flops are connected together, they form a register. A register is used for storing and shifting data from an external source. The data is in the form of 1s and 0s. A counter is a register that is able to count the number of clock pulses arriving at its clock input. A counter can be positive edge triggered (i.e. the input changes from low to high) or negative edge triggered (i.e. the input changes from high to low). An n-bit binary counter consists of n flip-flops and has 2n distinct states. A 3-bit binary counter consists of three flip-flops and has eight states (i.e. 2 3 =8). Figure shows the circuit diagram for a 3-bit binary counter consisting of T flip-flops. The output changes when the input detects a negative edged signal (i.e. the input changes from logic 1 to logic 0). The outputs of the counter are Q0, Q1 and Q2. Assuming the outputs are initially all at logic 0, Figure shows the timing diagram for the operation of the counter. Table shows the sequential truth table for the 3-bit binary counter.

5 BINARY COUNTERS Electronic counters consist of bistables connected so that they toggle, i.e. behave as t-type flip-flops, when the pulses to be counted are applied to their clock (CK) input. Counting is done in binary code, the binary digits (bits) 1 and 0 being represented by high and low states respectively of the bistable s outputs. Ripple Counter In Fig a, a 3-bit binary ripple (or asynchronous) counter is shown, consisting of three falling-edge triggered toggling flip-flops FF0, FF1 and FF2 in which the Q output of each one feeds the CK (T) input of the next. To explain the action, suppose that the outputs Q0, Q1 and Q2, which give the total count at any time, have all been reset to zero. On the falling edge [ab] of the first clock pulse applied to CK0 of FF0 shown in Fig 23.69b, Q0 switches from 0 to 1. The resulting rising edge [AB] of Q0 is applied to CK1 of FF1 which does not change state. So Q2=0, Q1=0 and Q0=1, giving a binary count of 001 after one pulse. The falling edge [cd] of the second clock pulse makes FF0 change second clock pulse makes FF0 change state again and Q0 flops from 1 to 0. The falling edge [CD] of Q0 switches FF1 this time, making Q1 = 1. The rising edge [LM] of Q1 leaves FF2 unchanged. The count is now Q2 = 0, Q1 = 1 and Q0 = 0, i.e. 010 in binary (2 in decimal). The falling edge [ef] of the third clock pulse to CK0 of FF0 changes Q0 from 0 to 1 again but the rising edge [EF] does not switch FF1, leaving Q1=1, Q2=0 and the count at 011 (3 in decimal). The action thus ripples along the flip-flops, each one waiting for the previous one to supply a falling edge at its CK input before changing state. The table in Fig c shows how the states of Q0, Q1 and Q2 give the count in binary of the clock pulses fed to CK0. Q0 being the least significant bit (l.s.b.) and Q2 the most significant bit (m.s.b.)