12/31/2010. Overview. 12-Latches and Flip Flops Text: Unit 11. Sequential Circuits. Sequential Circuits. Feedback. Feedback

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1 2/3/2 Overview 2-atches and Flip Flops Text: Unit equential Circuits et/eset atch Flip-Flops ECEG/IC 2 igital Operations and Computations Winter 2 r. ouie 2 equential Circuits equential circuits: Output depends upon current and past inputs Memory is required Two basic memory devices: atches Flip-flops Feedback is needed to store output state equential Circuits Flip-Flop Output changes based upon an input clock signal Used in signal generation atches Output changes based upon data input r. ouie 3 r. ouie 4 Feedback An output is fed to an earlier input Example of an inverter circuit Feedback Assume that there is a delay before the inversion is complete If the signal starts as, then: time r. ouie 5 r. ouie 6

2 2/3/2 Feedback A stable state (persistent or ) is not reached If another inverter is added, then the output is stable imilar to debounced switch et-eset atch Consider two NO gates In this configuration, they form a et-eset atch, for reasons shown hereafter P r. ouie 7 r. ouie 8 et-eset atch Present state: the state of at the time the signals are applied (or changed), Next state: the state of after the latch has reacted to the input, + et-eset atch If =, find + if == P r. ouie 9 r. ouie et-eset atch If =, find + if == P = ( + ) = ( + ) = + = ( + P) = ( + ) = Is this stable? et-eset atch If =, find + if == P = ( + ) = ( + ) = + = ( + P) = ( + ) = Is this stable? Yes! + = Next state P P = + = r. ouie r. ouie 2 2

3 2/3/2 et-eset atch Now assume that changes to By our notation: Next state on previous slide becomes the present state + on previous slide becomes What does the output become? et-eset atch Now assume that changes to = => P = ( + ) = => + = ( + ) = Present state Next state Present state Next state P = = P =? + =? P = = P = + = r. ouie 3 r. ouie 4 et-eset atch Changing from to changed the output from to Is this state stable? present state et-eset atch Changing from to changed the output from to Is this state stable? =, = P = ( + ) = + = ( + ) =, Yes it is stable present state P = = P = + = r. ouie 5 r. ouie 6 et-eset atch What if the is returned to? et-eset atch What if the is returned to? =, = P = ( +) = + = ( +) =, stable, no change in output present state present next P = = P = = P = + = r. ouie 7 r. ouie 8 3

4 2/3/2 et-eset atch et-eset atch Wait, I thought that when = =, the output was. What happened? For / atches, there are two possible stable outputs for each input, depending on the previous state of the latch ecap: tarted with =, =; output was (stable) Changed to ; output became (stable) Changed back to, output stayed at (stable) Changing to is known as setting the latch What happens now when =? r. ouie 9 r. ouie 2 et-eset atch What happens now when = ( = )? =, = + = ( + ) =, output returns to zero P = ( + ) = Is it stable? et-eset atch What happens now when = ( = )? =, = + = ( + ) =, output returns to zero P = ( + ) = Is it stable? P = ( + ) = = ( + ) =, yes! present next present next P = = P = + = P = = P = + = r. ouie 2 r. ouie 22 et-eset atch ecap: tarted with =, =; output was (stable) Changed to ; output became (stable) Changed back to, output stayed at (stable) Changed to, output reset to (stable) Changing to is known as resetting the latch What happens when = = (both setting and resetting the latch)? et-eset atch What happens when = = (both setting and resetting the latch)? P = ( + ) = (regardless of ) + = ( + P) = (regardless of ) Oscillations are possible if and change back to (depending propagation delays) Generally, we do not allow and to be equal to at the same time next P = + = r. ouie 23 r. ouie 24 4

5 2/3/2 et-eset atch et-eset atch With the limitations on the input states, stable states are always complements P = implified ymbol Timing iagram t t 2 t 3 t4 r. ouie 25 r. ouie 26 et-eset atch + = + (leave off the time index) Given that = eferred to as the characteristic or next-state equation (t) (t) (t) (t +e) X X witch ebouncing / can be used to make a debounced switch Pull down resistors are used for input Bouncing to the input to does not propagate through to, similar result for bounces +V b a r. ouie 27 r. ouie 28 ata input () and Gate input (G) When G =, the input to is passed through to When G =, does not change Known as a transparent latch Based on the description, let s populate the truth table How many columns to our truth table? r. ouie 29 r. ouie 3 5

6 2/3/2 Based on the description, let s populate the truth table How many columns to our truth table? G + When G =, the input to is passed through to When G =, does not change Complete the truth table G + r. ouie 3 r. ouie 32 When G =, the input to is passed through to When G =, does not change Complete the truth table G + The resulting K-map is shown What is the characteristic equation? G + G r. ouie 33 r. ouie 34 + = G + G G + G + = G + G ealization with / atch + = + = G = G + = G +(G ) = G +(G + ) = G+G + = G + G (consensus theorem) G r. ouie 35 r. ouie 36 6

7 2/3/2 Edge Triggered Flip-Flop ealization with / atch + = G + G G ymbol G Flip-flops change their output based upon a clock signal, Clock or Clk or ata input Output, ising Edge or Falling Edge are possible The edge (rising or falling) that triggers the operation is known as the active edge rising edge falling edge time r. ouie 37 r. ouie 38 Edge Triggered Flip-Flop ymbol for ising Edge ymbol for Falling Edge Edge Triggered Flip-Flop Truth table for edge-triggered Flip-Flop The output + is equal to the input just before the active edge + = + r. ouie 39 r. ouie 4 Edge Triggered Flip-Flop ealization of ising Edge Triggered Flip-Flop Falling Edge Flip-Flop G G r. ouie 4 r. ouie 42 7

8 2/3/2 ising Edge Flip-Flop ising Edge Flip-Flop Operation is time sensitive must be held at its value for a slight period before and after active edge t su : setup time (prior to active edge) t h : hold time (after active edge) t p : propagation delay (time from after an active edge to change in ) Example Inverter characteristics t p : 2ns Flip-Flop characteristics t su : 3ns t h : ns t p : 5ns Assume the clock period is 9ns clock r. ouie 43 r. ouie 44 ising Edge Flip-Flop ising Edge Flip-Flop Inverter characteristics t p : 2ns Flip-Flop characteristics t su : 3ns t h : ns t p : 5ns Assume the clock period is 9ns clock 9 ns 5 ns 2 ns et-up time of 3ns is not satisfied olution: increase clock period (decrease clock frequency) clock 9 ns 5 ns 2 ns 2 ns 2 ns r. ouie 45 r. ouie 46 ising Edge Flip-Flop ising Edge Flip-Flop et the clock period be 5 ns oes this work? clock et the clock period be 5 ns oes this work? Yes! et-up time of 3ns is satisfied Minimum clock period is ns clock 5 ns 5 ns 2 ns r. ouie 47 r. ouie 48 8

9 2/3/2 - Flip-Flop - Flip-Flop imilar in concept to atch = sets to = resets to can only change after clock active edge Truth table and characteristic equation is the same as an - latch, but + is interpreted differently + is the value of after the next active edge r. ouie 49 r. ouie 5 - Flip-Flop - Flip-Flop construction (master-slave) When CK = / set the master latch lave latch holds the previous value of - Flip-Flop When CK changes from to Output of the master latch is transferred to slave latch While CK =, the output does not change CK P Master P 2 slave 2 CK P Master P P P 2 slave 2 r. ouie 5 r. ouie 52 - Flip-Flop When CK changes from to value is latched in the slave New inputs to the master can be processed ee page 34 for a timing diagram Note how this is different from an edge-triggered flip-flop J/K Flip Flop imilar to - Flip-Flop J => K => J and K may both be changes from to or to on next active edge CK P Master P 2 slave 2 K J r. ouie 53 r. ouie 54 9

10 2/3/2 J/K Flip Flop J/K Flip Flop (rising edge) + = J + K J K + J K r. ouie 55 r. ouie 56 Used often in counters T input T (toggle) Flip-Flop Clock input T =, changes state after next active edge T =, no state change occurs T Flip-Flop + = T + T = T T + r. ouie 57 r. ouie 58 T Flip-Flop Implementation Connect the J and K inputs of a J/K flip flop together and connect that to T input Flip-Flops with Additional Inputs ee text ection.8 for more information K T J r. ouie 59 r. ouie 6