UNIVERSITI MALAYSIA PERLIS. EET107 Digital Electronics I [Elektronik Digit I]
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1 UNIVERSITI MALAYSIA PERLIS Peperiksaan Semester Kedua Sidang Akademik 2011/2012 Jun 2012 EET107 Digital Electronics I [Elektronik Digit I] Masa : 3 jam Please make sure that this question paper has FIFTEEN (15) printed pages including this front page and appendices before you start the examination. [Sila pastikan kertas soalan ini mengandungi LIMA BELAS (15) muka surat yang bercetak termasuk muka hadapan dan lampiran-lampiran sebelum anda memulakan peperiksaan ini.] This question paper has SIX (6) questions. Answer any FIVE (5) questions only. Each question contributes 20 marks. [Kertas soalan ini mengandungi ENAM (6) soalan. Jawab mana-mana LIMA (5) soalan sahaja. Markah bagi tiap-tiap soalan adalah 20 markah.] Note: Tie up Appendix 1 together with your answer script if you choose to answer any related question. [Nota: Ikatkan Lampiran 1 bersama-sama skrip jawapan anda sekiranya anda menjawab soalan yang berkaitan.]
2 Question 1 [Soalan 1] a) The numbers given below are represented in BCD code. Convert both numbers into Hexadecimal number and do addition operation. Illustrate your final answer in binary number. [Nombor-nombor yang diberikan di bawah adalah dalam kod BCD.Tukarkan nombor - nombor tersebut ke nombor perenambelasan dan lakukan operasi penambahan. Tunjukkan jawapan akhir anda di dalam nombor perduaan.] (6 marks / markah) b) Figure 1 shows a logic circuit for the current system in coffee mix factory. There are three main sensors (A, B and C) used in this system for packaging. As an engineer, you need to simplify the system design. [Rajah 1 menunjukkan satu litar logik untuk sistem sedia ada di kilang campuran kopi. Terdapat tiga penderia utama (A, B dan C) yang digunakan dalam sistem ini untuk pembungkusan. Sebagai seorang jurutera, anda dikehendaki permudahkan rekabentuk sistem tersebut. ] i) Based on the current system logic diagram, develop the truth table for the system. [Berpandukan pada litar logik sistem sedia ada, binakan jadual kebenaran untuk sistem tersebut.] (5 marks / markah) ii) Derive the simplified Boolean expression for output, Y, using Karnaugh map. [Terbitkan ungkapan Boolean termudah untuk keluaran, Y, menggunakan peta Karnaugh.] (5 marks / markah) iii) Sketch the simplified logic circuit. [Lakarkan litar logik termudah.].3/-
3 - 3 - Figure 1 [Rajah 1].4/-
4 Question 2 [Soalan 2] a) Consider the following Karnaugh map that is shown in Figure 2(a) for the function F (W, X, Y, Z). [Pertimbangkan peta Karnaugh yang ditunjukkan dalam Rajah 2(a) untuk fungsi F (W, X, Y, Z).] i) Derive the minimum Product-Of-Sum (POS) expression for function F (W, X, Y, Z). [Terbitkan ungkapan pendaraban hasil tambah (POS) yang minima untuk fungsi F (W, X, Y, Z).] ii) Sketch the circuit that corresponds to the POS expression from a(i) using NAND gates only. [Lakarkan litar berdasarkan pada ungkapan POS dari a(i) menggunakan get-get TAK-DAN sahaja.] Figure 2(a) [Rajah 2(a)].5/-
5 - 5 - b) Figure 2(b) shows a combinational logic circuit that consist of three inputs, A, B and C, and one output, F (A, B, C). Based on the circuit given: [Rajah 2(b) menunjukkan satu litar logik gabungan yang mempunyai tiga masukan, A, B, dan C, dan satu keluaran, F (A, B, C). Berdasarkan litar yang diberi:] i) derive Boolean expression for output F (A, B, C) and minimize the expression using Boolean algebra and DeMorgan s theorems. [terbitkan ungkapan Boolean untuk keluaran F (A, B, C) dan permudahkan ungkapan tersebut menggunakan teorem Boolean algebra dan DeMorgan.] (5 marks / markah) ii) write standard Product-of-Sum (POS) expression for function F (A, B, C) using truth table. [tuliskan ungkapan piawai pendaraban hasil tambah (POS) untuk fungsi F (A, B, C) menggunakan jadual kebenaran.] (3 marks / markah) iii) sketch the circuit for the simplified expression in b(i) using NOR gates only. [lakarkan litar untuk ungkapan termudah dalam b(i) menggunakan get-get TAK- ATAU sahaja.] Figure 2(b) [Rajah 2(b)].6/-
6 Question 3 [Soalan 3] a) A half adder is a combinational logic circuit that has two inputs, X and Y, and two outputs, Sum and Carry Out, resulting from binary addition of X and Y. [Penambah separuh adalah sebuah litar logik gabungan yang mempunyai dua masukan, X dan Y, serta dua keluaran, Jumlah dan Bawa Keluar, terhasil dari penambahan asas perduaan X dan Y.] i) Design a half-adder as a two level AND-OR circuit. [Rekabentuk satu penambah separuh sebagai litar DAN-ATAU dua peringkat.] (6 marks / markah) ii) Show how to implement a full adder by using half adder. [Tunjukkan bagaimana untuk melaksanakan penambah penuh dengan menggunakan penambah separuh.] (2 marks / markah) b) Figure 3 shows a server room plan. A new air conditioning system needs to be designed for the sever room. The room requires a cool temperature as the servers are too sensitive with high temperature. The room temperature is monitored by 2-bit sensors which are sensor A and sensor B. Two units of air conditioner are provided in order to make system functions, ON and OFF according to Table 3. [Rajah 3 menunjukkan satu pelan bilik pelayan. Satu sistem penyaman udara baru perlu direkabentuk untuk bilik pelayan tersebut. Bilik tersebut memerlukan suhu yang rendah memandangkan pelayan sangat sensitif dengan suhu yang tinggi. Suhu bilik akan dipantau oleh penderia 2-bit iaitu penderia A dan penderia B. Dua unit penyaman udara disediakan untuk memastikan sistem berfungsi, BUKA dan TUTUP berdasarkan Jadual 3.] i) Design the system with consideration to the operational condition of both air conditioners as shown in Table 3. Complete the design with a truth table, a Karnaugh map, the Boolean expression and the simplified logic circuit. [Rekabentuk sistem tersebut dengan mempertimbangkan keadaan operasi kedua- dua penyaman udara seperti yang ditunjukkan pada Jadual 3. Lengkapkan rekabentuk tersebut dengan jadual kebenaran, peta Karnaugh, persamaan Boolean dan litar logik termudah.] (10 marks / markah) ii) Recommend an alternative method or system that can do the same function as the situation above. [Cadangkan satu kaedah atau sistem alternatif yang dapat melakukan fungsi sama seperti keadaan di atas.] (2 marks / markah).7/-
7 - 7 - Figure 3 [Rajah 3] Table 3 [Jadual 3] Condition of Temperature Sensor A > sensor B Sensor B > sensor A Sensor A = sensor B Operation Air Conditioner 2 ON Air Conditioner 1 ON Both Off.8/-
8 Question 4 [Soalan 4] a) Errors can occur as digital codes are being transferred from one point to another within a digital system or codes are being transmitted from one system to another. The Parity Generator as shown in Figure 4(a) does not function as you wish. As an engineer, you need to design a digital system that generates ODD Parity to your 6 bits codes (A 5, A 4, A 3, A 2, A 1 and A 0 ). Predict and state the problem with the circuit and draw the correct circuit. [Ralat boleh berlaku ketika kod digit dipindahkan dari satu titik ke titik yang lain dalam sistem digit atau kod yang dipancarkan dari satu sistem ke sistem yang lain. Penjana Kesetarafan yang ditunjukkan dalam Rajah 4(a) tidak berfungsi seperti yang anda kehendaki. Sebagai seorang jurutera, anda dikehendaki untuk merekabentuk satu sistem digit yang menjana Kesetarafan GANJIL terhadap kod 6 bit (A 5, A 4, A 3, A 2, A 1 dan A 0 ) anda. Ramalkan dan nyatakan masalah yang terdapat dalam litar tersebut dan lukiskan litar yang betul.] Figure 4(a) [Rajah 4(a)].9/-
9 - 9 - b) Multiplexer (MUX) is also called data selector which is a device that allows digital information from several sources to be routed onto a single line for transmission over that line to a common destination. The selection of a particular input line is controlled by a set of input variables, called selection inputs. A block diagram of an 8:1 MUX is shown in Figure 4(b). [Pemultipleks (MUX) juga dipanggil sebagai pemilih data adalah peranti yang membenarkan maklumat digit dari beberapa sumber untuk dilalukan pada talian penghantaran tunggal ke destinasi sepunya. Pemilihan masukan tertentu dikawal oleh set pembolehubah masukan, dipanggil masukan pemilihan. Sebuah gambarajah blok MUX 8:1 ditunjukkan dalam Rajah 4(b).] i) Develop the truth table that implements the 8:1 MUX shown in Figure 4(b). [Binakan jadual kebenaran yang melaksanakan MUX 8:1 seperti ditunjukkan dalam Rajah 4(b).] (6 marks / markah) ii) State the function F (W, X, Y, Z) in small m notation and write the standard Sum-of-Product (SOP) expression for the function. [Nyatakan fungsi F (W, X, Y, Z) dalam tatatanda m kecil dan tuliskan ungkapan piawai penambahan hasil darab (SOP) bagi fungsi tersebut.] Figure 4(b) [Rajah 4(b)].10/-
10 c) Figure 4(c) shows the MUX-DEMUX connection. The four inputs of the multiplexer and selector for MUX-DEMUX connection will receive the input data as shown in Figure 4(d). Based on the given input data, analyse the circuit and sketch the output waveforms for each output, W, X, Y and Z. Use Appendix 1 to sketch the outputs. [Rajah 4(c) menunjukkan sambungan MUX-DEMUX. Empat masukan pemultipleks dan pemilih untuk sambungan MUX-DEMUX akan menerima data masukan seperti ditunjukkan dalam Rajah 4(d). Berdasarkan data masukan yang diberi, analisa litar tersebut dan lakarkan gelombang-gelombang keluaran untuk setiap keluaran, W, X, Y, dan Z. Gunakan Lampiran 1 untuk melakar keluaran-keluaran.] (6 marks / markah) Figure 4(c) [Rajah 4(c)] Figure 4(d) [Rajah 4(d)].11/-
11 Question 5 [Soalan 5] a) Table 5 shows the input-output mapping for 7-segment decoder. The alphabets output of 7-segment decoder is given in Table 5 and represented in ASCII code. Convert the message into 8-bit binary numbers. Use Appendix 2 for ASCII code. [Jadual 5 menunjukkan pemetaan masukan-keluaran bagi penyahkod 7-ruas. Huruf-huruf keluaran penyahkod 7-ruas diberikan dalam Jadual 5 dan diwakilkan dalam kod ASCII. Tukarkan mesej tersebut ke nombor perduaan 8-bit. Gunakan Lampiran 2 untuk kod ASCII.] Table 5 [Jadual 5] W X Y Z E r F o b d C Blank.12/-
12 b) A 7-segment decoder will accept 3-bit binary input and the input will then be displayed on the 7-segment display. Figure 5 shows a block diagram for decoder of 3-bit binary to 7-segments display. [Sebuah penyahkod 7-ruas akan menerima masukan 3-bit perduaan dan masukan tersebut akan dipaparkan pada paparan 7-ruas. Rajah 5 menunjukkan gambarajah blok untuk penyahkod 3-bit perduaan ke paparan 7- ruas.] i) Generate the truth table for the 7-segment outputs of the alphabets to be displayed as shown in Table 5. Unused output is blanked. [Hasilkan jadual kebenaran untuk huruf-huruf keluaran 7-ruas yang akan dipaparkan seperti ditunjukkan dalam Jadual 5. Keluaran yang tidak digunakan tidak dipaparkan.] ii) Derive the simplified Boolean expression for each segment using Karnaugh map. [Terbitkan ungkapan Boolean termudah untuk setiap ruas dengan menggunakan peta Karnaugh.] (7 marks / markah) iii) Sketch the simplified decoder logic circuit. [Lakarkan litar logik penyahkod termudah.] (5 marks / markah) Figure 5 [Rajah 5].13/-
13 Question 6 [Soalan 6] a) A circuit for 4-bit asynchronous binary counter is shown in Figure 6. Each J-K flip-flop is positive edge-triggered. Based on the given circuit, sketch an asynchronous counter that can be implemented having a Modulus-14 with a binary sequence from 0000 through [Satu litar pembilang perduaan 4-bit tak segerak ditunjukkan dalam Rajah 6. Setiap flip-flop J-K adalah picuan pinggir positif. Berdasarkan litar yang diberi, lakarkan satu pembilang tak segerak yang boleh dilaksanakan dengan mempunyai Modulus-14 yang menunjukkan jujukan perduaan dari 0000 hingga 1101.] Figure 6 [Rajah 6] b) Design a Modulus-8 synchronous counter that will count down 8 numbers, which starts from 7 10 (111 2 ) to 0 10 (000 2 ) and count back to 7 10 (111 2 ). Use positive edgetriggered D flip-flops. [Rekabentuk satu pembilang segerak Modulus-8 yang akan mengira secara menurun sehingga 8 nombor, yang bermula dari 7 10 (111 2 ) hingga 0 10 (000 2 ) dan mengira semula dari 7 10 (111 2 ). Gunakan flip-flop D berpicu pinggir positif.] i) Sketch the state diagram and develop the state table. [Lakarkan gambarajah keadaan dan binakan jadual keadaan.] (5 marks / markah) ii) iii) Derive the minimum Boolean expression for each flip-flop using Karnaugh maps. [Terbitkan ungkapan Boolean yang minima untuk setiap masukan flip-flop dengan menggunakan peta-peta Karnaugh.] (5 marks / markah) Construct the complete circuit for a Modulus-8 synchronous counter. [Bina litar yang lengkap bagi pembilang segerak Modulus-8.] (6 marks / markah).14/-
14 Appendix 1: [Lampiran 1:] Question 4(c) [Soalan 4(c)] Angka Giliran:. No. Meja :..15/-
15 Appendix 2: [Lampiran 2:] Question 5(a) [Soalan 5(a)] Angka Giliran:. No. Meja :. Data sheet for ASCII code -ooooooo-
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