Digital Correction for Multibit D/A Converters

Transcription

1 Digital Correction for Multibit D/A Converters José L. Ceballos 1, Jesper Steensgaard 2 and Gabor C. Temes 1 1 Dept. of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR 97331, USA 2 ESION LLC, Carlsbad, CA 9218, USA ceballos@ece.orst.edu ABSTRACT This paper presents simulation results for a novel calibration scheme used to improve the high-speed digital-to-analog converters (DACs) linearity. This mixed-signal technique has only one analog element as main interface in its simplest form (a latched comparator). The use of digital correlation to acquire the DAC unit element s errors, plus the use of a reducedscale auxiliary DAC, allows linearity improvements of more than 5 bits (~3 db). Keywords: DAC, adaptive correction. 1. INTRODUCTION Multibit delta-sigma ( Σ) digital-to-analog converters (DACs) are widely used in audio, wireless and wireline communication systems. They contain a digital interpolation filter, a noise-shaping loop which reduces the wordlength of the digital signal, a low-resolution internal DAC, and an analog smoothing filter. Such converters are capable of very high accuracy and linearity, up to 2 bits or even higher. A major limitation of such converters is the achievable static linearity of the embedded DAC. For Σ DACs with narrow-band signals, the effective DAC linearity can be vastly improved by using a high oversampling ratio (OSR) combined with a dynamic element matching (DEM) method [1]. However, for DACs processing wideband signals, such as occurring in communication applications, the OSR is restricted to low values by the limited speed capability of the analog circuitry used. In this situation, DEM does not provide enough accuracy improvement for a high (say, 15 or more ENOB) linearity for the overall converter. In this paper, an alternative approach is described for achieving enhanced DAC accuracy. It uses an adaptive digital correction of the internal DAC. The process is based on acquiring and refining digital estimates for the errors of all unit elements (capacitors or current sources) which form the internal DAC, and then applying the appropriate corrections to the output signal according to the known usage of these elements. Numerical simulations verified that even for large initial errors, a very high conversion accuracy can be achieved using the proposed algorithm. 2. THE CORRECTION OF THE DAC The correction system is depicted schematically in Fig. 1. The main components of the system are the main DAC (composed of 2 n = N unit elements), an auxiliary (reduced scale) DAC, 2 banks of registers (BANK 1 to store the individual errors, and BANK 2 to store the complete errors for the different codes), a scrambler to randomize the use of the unit elements, and associated logic. Fig. 1: schematic representation of the whole system. The signal processing block may contain an interpolator and a modulator to improve the ENOB (at expenses of speed)

2 The operation of the system can be described as follows: first, the digital input is preprocessed. Data are passed through an interpolation filter and a digital Σ loop, improving the Effective Number of Bits (ENOB). At the same time (in a parallel process) a Pseudo-Random Code is generated for a generic middle code. Considering a bipolar operation, the middle code is the zero code and it corresponds to the use of only half (N/2) of the total unit elements that compose the Main DAC. Also, this code will select the corresponding registers in BANK 1 (line SEL) to perform an addition with. This operation is realized in advance, that means once the addition is completed then the system will wait until a middle code appears. At this point the digital value of the addition will be converted to an analog one (by means of the Auxiliary DAC), the Main DAC will use the corresponding elements (signal SEL will be copied to SEL 1 and will command the Scrambler), and a comparison will be performed. It should be noted that the Scrambler will select the corresponding elements in the Main DAC only if SEL 1 is active, and this will occur if and only if the code is the middle one (signal EQ active) and at the same time the addition in BANK 1 is completed (signal ACK). After this occurs, the 1-bit comparison will tell whether the corresponding registers in BANK 1 must be increased or decreased. In BANK 2 the registers will be modified as follows: referring to Fig. 1, it is shown that the first register of BANK 2 will contain the error corresponding to the first element in the Main DAC, the second register will contain the error for the 1 st and the 2 d elements added together, an so on, until the last register which will contain the error of the sum of all the unit elements. When a specific unit element is used, then in accordance with the comparator output, the registers in BANK 2 that contain this element will be increased or decreased. The idea behind this procedure is that if the error is reduced each time when the comparison is carried out, that means that in steady state the registers in BANK 1 will contain a scaled version of the errors of the unit elements. If the registers in BANK 1 and BANK 2 have been updated in the same way and at the same time, then BANK 2 will contain the scaled estimate of the errors for the 2 n possible combinations (digital codes without being scrambled) for the sum of unit elements of the Main DAC. If the code is not the middle one or the system is busy, then the Auxiliary DAC will feed the corresponding output from BANK 2 (passing it trough a Multiplexer), and the correction will be performed. When the addition and the update of the registers in BANK 1 and BANK 2 is completed, then a signal (STRB) indicates that the registers are ready to perform another operation. Fig. 2: Another possible architecture, suitable for a totally analog implementation. The integrators could be implemented using switched current techniques to facilitate the additions (speed up the process). The total number of registers is 2N. The delay in the Analog/Digital loop is minimized with the use of the MUX. Another implementation is depicted schematically in Fig. 2. In this case, there are only N registers that are combined in the same way than was previously described: half of them will be considered for comparison/updating when the middle code appears (signal used in conjunction with signals S i from the SCRAMBLER block). The main difference now is that these registers can be analog memories (capacitances), and the Main and the Auxiliary DAC can be combined in only one device. Each analog memory could be the gate capacitance of an auxiliary current source in parallel with each one of the unit-element current sources of the Main DAC. Clearly the Auxiliary DAC is absorbed in the main one. In this configuration, because an addition is needed (no MUX involved) a delay is added in the feedback path if the processing is a mixed signal one (A/D). If the processing is only analog, the system is faster. Of course, if low speed operation is allowed, then DEM could be also applied, improving the effectiveness of the algorithm. 3. ANALYSIS In this paragraph a linear model will be considered for the topology. Consider only the output in the Middle- Code time points. It will be shown that the correction loop acts similar as a delta modulator for the Main DAC error. First of all define the following: E=[e 1,e 2, e N ] is the vector of individual errors in the Main DAC. Ê=[ê 1, ê 2, ê N ] is the vector of individual error estimates. =[δ 1, δ 2 δ N ] is the vector of differences defined as δ i =e i -ê i

3 Ê and E are vectors with the special property that in each one, one half is subtracted from the other half randomly and there is also a one-to-one correspondence between their used elements. An equivalent model for correction of the i-th error is shown in Fig. 3. In this case, it can be seen all the other element error differences act as a noise signal in the forward path of a delta modulator. Considering digital integrators (counters), dead zones can be introduced. The idea is to perform a wired truncation, discarding the LSBs of the counters, as depicted in Fig. 4. This has as advantage the decrease in the sensitivity. In the following ideal model no dead zones introduced by digital truncation effect were considered, as is the case for an analog-only processing scheme, but the variation in gain was taken into account. The gain G is the gain due to the truncation and the gain in the Auxiliary Digital-to- Analog converter. In both cases it is much lesser than 1. Fig. 5: Schematic of the system under locking conditions. G 1: Truncation gain, G 2: gain of the AUX-DAC Fig. 6: CMP in is the input to the comparator in the middle code. 2-bit system The feedback loop forces the signal before the comparator to zero. In locking conditions, the system can be depicted as in Fig. 5. When correction/estimation is performed, one can draw an equivalent diagram such as the one depicted in Fig. 6. In this, each φ i signal can be - 1 or +1, indicating that randomly half of the unit elements are in the positive side, and the other half in the negative one. We can then write Fig. 3: Equivalent model for one of the errors in the middle code operating point and its lineralized model. i i 2 Φ i = ± 1 Φ i = 1 ; Φ = (1) The output of this system (CMP in ), which represents the input to the comparator, in the middle-code points (for a 2-bit example) is given by CMPin = ( e1 eˆ 1) Φ 1 + ( e2 eˆ 2) Φ2 + ( e3 eˆ 3) Φ3 + ( e4 eˆ 4) Φ4 (2) With the following characteristics: Fig. 4: Truncation in the registers. It is equivalent to a dead zone plus a gain scaling. E V { CMPin} = { CMPin} = V{ ( ei eˆ i) Φi} i Here, E{.} and V{.} are the expected value and the variance operators respectively. It can be easily shown that (3)

4 1.5 x 1-5 Estimated error Original error Residual error 1.5 (2) (2) + offset Error [A] Unit Element # Fig. 7: Example for a 2-bit current-steering corrected system. Registers S i (i=1..4) store the individual errors; registers S j (j=a E) store the error for the 5 different digital codes. 1 x (a) V {( ei eˆ i) Φi} = V{ eˆ i} (4) If the variance of ê i is limited by the step of the AUX- DAC, and considering Gaussian distributions, the maximum values of the deviation can be estimated. Instead of doing that, and because of the presence of the dead zones, the procedure of simulation and observation was followed. As another point of view, the whole system can be thought as a CDMA system, but in a closed loop, with the quantization noise equivalently considered as the channel noise. 4. SIMULATION RESULTS In this section the simulated results for a fully differential topology (similar to the one in Fig. 7) will be presented. A 3-bit (n = 8) modulator was assumed. A zerooptimization procedure was used to reduce the in band quantization noise of the Σ modulator in the design stage. An over-sampling ratio (OSR) 8 and an eightorder structure were employed. The initial errors, the estimated errors and the residual errors are shown in Fig. 8; Fig. 9 shows the variation in the counters around their mean value. For a 3-bit system (with inclusion of nonidealities during the simulation), proving the concept of Gaussian distributions. The dead zones introduced by the truncation operation are helpful in diminishing this effect. The FFTs of the output before and after correction are shown in Fig. 1. error(unit Values[i]) - STATE[i] * Gain Sample # (b) Fig. 8: a) Original, estimated and residual errors for a 3 bit converter. b) Time convergence for the eight elements Fig. 9: Histograms of counter outputs for the 8 unit elements around their mean value after convergence. Full randomization was used. x 1 4

5 Performance of the ideal system [db] FFT of the output signal. Noise Power vs. Signal Bandwih Fig. 11: Layout of the prototype. -2 Performance of the adaptive DAC - No correction 5. EXTRA DESIGN CONSIDERATIONS AND LAYOUT [db] FFT of the output signal. Noise Power vs. Signal Bandwih Performance of the adaptive DAC3 system after convergence -2-4 The use of a reduced set of pseudo-random middle codes can be considered. Although it will not be described here, it can be shown that this reduction can lead to a very fast and robust architecture. Having a fixed number of middle codes is equivalent of having a fixed (and reduced) number of possibilities; hence, there is no need of additions (no adder!). The codes can be wired to a new block of memory, and their outputs can be used through another MUX. The previous ideas have been implemented in a CHIP (now in fabrication), using a 2P4M.35µm technology. Fig. 11 shows the layout of the prototype device. -6 [db] CONCLUSIONS AND REMARKS FFT of the output signal. Noise Power vs. Signal Bandwih Fig. 1: Output FFT of the 3-bit ideal system (a), before (b) and after (c) correction, for a -3dB input signal. Note the increase of the SFDR in c). In the simulations, return-to-zero (RZ) input signal was used in order to force the middle code periodically. This has two advantages: first of all, a DC signal can be processed, and the dynamic performance is also improved using this technique, although jitter can degrade the SNR. For high-frequency designs it is important to isolate the channels (increase the SFDR). Then, the increase of the in-band noise floor due to jitter is of less concern [2]. A new technique was simulated for the correction of a high-speed DAC. Simulations were carried out for a current-steering topology. SFDR values higher than 1dB were obtained, even considering nonidealities such as comparator noise and offset, resistor mismatches and nonlinearities in the Auxiliary DAC. As previously mentioned, the comparator is the most sensitive block of the system. Hence, a 3-stage autozeroed latched comparator was specially designed. The idea is to have enough gain to overcome the inherent offset of the latch, and at the same time to have high speed. Considering this last item, the integrated input noise (mainly thermal) acts as dither, and because of the averaging nature of the whole correction process, it has no effect on the steady-state results. In order to achieve rapid convergence, the equivalent noise bandwih can be manipulated by changing the capacitive load seen by the first stage of the comparator.

6 5. ACKNOWLEDGEMENTS The authors want to thank CDADIC (NSF Center for Design Analog-Digital Integrated Circuits), and Analog Devices (ADI), for funding the project. 6. REFERENCES [1] R. T. Baird & T. S. Fiez, Improved Σ DAC Linearity using Data Weighted Averaging, Proc IEEE Int. Symp. Circuits Syst., vol. 1, pp , May [2] J. Hyde, T. Humes, C. Diorio, M. Thomas & M. Figueroa, A 3-MS/s 14-bit Digital-to-Analog Converter in Logic CMOS, IEEE JSSC, vol. 38, no. 5, pp , May 23.