Radar Signal Processing Final Report Spring Semester 2017

Transcription

1 Radar Signal Processing Final Report Spring Semester 2017 Full report report by Brian Larson Other team members, Grad Students: Mohit Kumar, Shashank Joshil Department of Electrical and Computer Engineering Colorado State University Fort Collins, Colorado Project advisor(s): Dr. V. Chandrasekar Approved by: Mohit Kumar 1 P a g e

2 Abstract Currently the D3R radar is an important part of the Global Precipitation Measurement mission. It is used to gather data for the Ground Validation program, which uses data from several radars to cross-validate to characterize errors and quantify uncertainties in the precipitation measurements of the GPM program [1]. Currently this radar uses a Pentek Model board for signal processing. This board includes three input channels of analog to digital converters (ADC) and two output digital to analog converters (DAC). It also includes a Xilinx Virtex-6 field programmable gate array (FPGA). The issue is that only two of the three input channels are active. This is because the team previously working on the FPGA digital processing design was not able to fit the required logic for all three input channels. The first thing we did was start building the signal processing blocks from scratch with resource management and efficiency in mind. This allowed us to learn how to design parts that utilized the FPGA s resources more effectively from the start. We are utilizing Xilinx IPcores in this design because it was specifically designed to be optimized for the FPGA. This is because there are some specialized parts in the Virtex-6 FPGA that can only be effectively utilized by the IPcores. The next stage of the project was to modify the existing FPGA design to work with all available input channels. This involved modifying several VHSIC Hardware Description Language (VHDL) code blocks. There were control registers that needed to be expanded to hold the additional control information as well as data flow changes. 2 P a g e

3 Contents Abstract... 2 Contents... 3 Table of Figures... 4 Chapter 1: Introduction... 5 Chapter 2 Review of Previous Work Analog to digital converter interface Direct Digital Synthesizer (DDS) Finite Impulse Response (FIR) Filter Pulse Compression Filter... 9 Chapter 3 VHDL Changes Control Registers DSP Subchannel Subchannel-Interleaver Chapter 4 Tools Xilinx ISE Xilinx ISim MATLAB Chapter 5 Optimization Synthesis Implementation Chapter 6 Testing and debugging Chapter 7 Conclusions and Future Work References Appendix A: Abbreviations Appendix B: Budget Appendix C: Timeline Original timeline Revised Timeline Acknowledgments P a g e

4 Table of Figures Figure 1 - Pentek Model [2]... 5 Figure 2 - Pentek Virtex 6 FPGA [2]... 5 Figure 3 - ADC Acquisition Module [2]... 6 Figure 4 - Digital Downconverter... 7 Figure 5 - ADS5485 timing information [3]... 7 Figure 6 - DDS Phase Accumulator [6]... 8 Figure 7 - Downconverter output given 70Mhz input... 8 Figure 8 - Pulse Compression Filter diagram P a g e

5 Chapter 1: Introduction The D3R radar is an important part of the Global Precipitation Measurement (GMP) mission. It is used to gather data for the Ground Validation program, which uses data from several radars to cross-validate to characterize errors and quantify uncertainties in the precipitation measurements of the GPM program [1]. This radar currently uses a Pentek Model board for initial signal processing and interfacing with servers. This board includes three input channels of analog to digital converters (ADC) and two output digital to analog converters (DAC). The three analog to digital converters are intended to be used to read radar inputs. Two of these channels are used to measure active polarized radar inputs and matching polarized outputs. The issue is that only two of the three input channels are currently in use. This is because the team previously working on the FPGA digital processing design was not able to fit the required logic for all three input channels. Implementing an additional analog to digital converter channel will significantly improve the accuracy of the overall system. The additional channel will be used mainly as a passive sensor. This will to help filter out noise that could otherwise impact the accuracy of the other two sensors. The result of this is better weather analysis and prediction. A major benefit of this project is that it should have no additional cost for new hardware. In this project, we will make use of the existing hardware to add additional functionality. By adding the passive channel with the current hardware, there will be less need to upgrade it. By delaying a hardware upgrade to the digital receiver and waveform generator, other parts of the radar may be upgraded. Pentek provided board as well as the base infrastructure for the FPGA. The basic block diagram of the board can be seen in Figure 1 - Pentek Model The board provides the interface between the radars and the servers. Figure 2 - Pentek Virtex 6 FPGA shows a block diagram of the provided FPGA code. As you can see there are the expected three 200MHz 16 bit inputs as well as the two outputs as well as a PCI-E interface to communicate with servers. Figure 1 - Pentek Model [2] Figure 2 - Pentek Virtex 6 FPGA [2] 5 P a g e

6 Inside the ADC Acquisition Modules there is a section of user code as seen in Figure 3 - ADC Acquisition Module. This is where the focus of this project lies. In this section, we will be implementing a digital downconverter and a pulse compression filter. Figure 3 - ADC Acquisition Module [2] In this project, we will focus on creating a less resource intensive design for signal processing inside the FPGA. The two main challenges in this project are to create a design that fits in the FPGA and meets timing. To do this we will balance the utilization of the different parts of the design. One example of this could be to reduce the number of values in the coefficient vector in the finite impulse response filter (discussed in chapter 2). The first thing we did was start building the user block from scratch with resource management and efficiency in mind. This allowed us design parts that were more efficient from the start. We are utilizing Xilinx IPcores in this design because it was specifically designed to be optimized for the FPGA. This is because there are some specialized parts in the Virtex-6 FPGA that can only be effectively utilized by the IPcores. Chapter 2 contains a review of previous work. 6 P a g e

7 Chapter 2 Review of Previous Work The major part we designed up to this point is the Digital Downconverter. The design of the downconverter can be seen in Figure 4 - Digital Downconverter. The downconverter is designed to read in a 60 MHz signal with a 30MHz bandwidth, then shift it down to baseband. Due to the ADC only having a real-time component and no imaginary component, the output signal will have a reflection. This reflection, along with all the high frequency noise, will be filtered out of the signal. Figure 4 - Digital Downconverter 2.1 Analog to digital converter interface In this project, we will interface with the ADS Bit, 200-MSPS Analog-to-Digital Converter (ADC). This ADC sends information over 16 pins using differential signaling. This means that there are 8 differential pairs sending data. Differential pairs are used to reduce the interference from external electromagnetic interference. Because there are only 8 signals being sent at a time, the ADC sends two sets of information each clock cycle as seen in Figure 5 - ADS5485 timing information. It sends the even bits on the rising clock edge and the odd bits on the falling clock edge. To use this data, we need to repack it as a single 16-bit value. To accomplish this, we saved the even bits of data on the rising clock edge, stored the value and packed it with the odd bits of data. We would then output this value on the next rising clock edge while also reading in the next set of even bits. Figure 5 - ADS5485 timing information [3] 7 P a g e

8 2.2 Direct Digital Synthesizer (DDS) The first part of the downconverter is the 60MHz DDS. The function of the DDS is to generate sign and cosine wave to represent the real and imaginary domains. By multiplying the output of the DDS by the input from the ADC, the signal is shifted down by 60MHz. The DDS functions by using a Phase Accumulator to control the address it needs to use from the lookup table. This way it can output the closest digital value to the sign wave it is generating. For this project we used the Xilinx Figure 6 - DDS Phase Accumulator [6] LogiCORE IP DDS Compiler v4.0. This is a highly customizable design, which we used to output a 60MHz 16-bit two s complement signal. Using the Xilinx DDS datasheet [4], we could set up all the parameters. 2.3 Finite Impulse Response (FIR) Filter After the signal has been shifted down, we used a FIR filter as a downconverter to filter out any frequencies above 15MHz. This filtering is done in the real-time domain using the equation M h[k]x[n k] k= M. We used the Xilinx IP LogiCORE FIR Compiler v5.0. We set it up to use a single channel, with two data streams to account for both the real and imaginary components of the signal. The output of this filter gave us a signal with no reflection and low noise. An example of this can be seen in Figure 7 - Downconverter output given 70Mhz input. Figure 7 - Downconverter output given 70Mhz input 8 P a g e

9 2.4 Pulse Compression Filter Pulse compression filters are used to increase the bandwidth of a pulse, improve sensitivity, and avoid sacrificing range resolution. If multiple responses overlap, a pulse compression filter allows you to measure the response time. X re[i] FIRre FIRre + - The pulse compression filter used in this project is shown in Figure 8 - Pulse Compression Filter diagram. X im[i] FIRim FIRim Figure 8 - Pulse Compression Filter diagram 9 P a g e

10 Chapter 3 VHDL Changes The Digital Signal Processing (DSP) block contains several major sections. It contains three DSP Subchannel, which control the processing for each of the three input channels. It also contains a subchannel-interleaver, which is used to control which Subchannel is currently sending processed data. The last major component is the DSP control registers Control Registers The Control Registers control how the incoming data is processed. There are multiple options for which filters are used for the digital downconverter in each DSP Subchannel. It is also possible to load a different set of coefficients into the pulse compression FIR filters. The control registers can be set to determine what options are selected in each of the DSP Subchannels at run time. The largest part of the control register is a block ram, which stores all control data. This block ram was expanded to hold the required control data for the new DSP Subchannel. It was also necessary to increase the width of the data bus which is used to send data back to servers for additional processing. 3.2 DSP Subchannel Each Subchannel is responsible for processing an input signal from the ADC. This signal goes through a digital downconverter to shift the signal to approximately 0 MHz. Once the signal is shifted it goes through a pulse compression filter. Finally, it is sends the processed signal to an output FIFO. 3.3 Subchannel-Interleaver The Subchannel-Interleaver is a block which controls when the Subchannels output their data. The Subchannel-Interleaver is controlled by the Control Registers. 10 P a g e

11 Chapter 4 Tools There were several modern tools used in this project. The main ones were Xilinx ISE, Xilinx ISim, and Matlab. All of these tools were used in conjunction. 4.1 Xilinx ISE The main tool used for this project was Xilinx ISE. It integrates with all other necessary Xilinx tools and contains all required functionality to work with the Virtex-6 FPGA. It contains a functional logic simulator, synthesis tool, layout mapper, and a bit-stream generation tool. There is also a very large IP library available to use. ISE is also able to tell whether or not your design meets the given timing and space constraints. ISE was also used because it can provide debugging tools such as ChipScope. Using ChipScope allows you to record the values of any bus you set inside the FPGA while it is running. It can start recording given a variety of different triggers. This can be very useful to track down any potential issues. 4.2 Xilinx ISim ISim is the functional simulation built into ISE. It was extremely helpful to track down bugs in the logic of the design. The most useful part of ISim is the waveform viewer. It allows you to track down most bugs much more easily. It is also a great tool for debugging. Although ISim is not able to directly export the values of its waveforms, we found a way to use VHDL to print the values of different busses to a file, which we would then open in Matlab MATLAB We have used MATLAB to plot the outputs to our design and verify it functions properly. We checked that our outputs were correct by plotting in both the time and frequency domains. An example of an output is shown in Figure 7 - Downconverter output given 70Mhz input. As you can see the output signal is 10MHz. 11 P a g e

12 Chapter 5 Optimization Most optimization was done using the Xilinx ISE Synthesize and Implementation tools. There are numerous settings for each step of the synthesis and Implementation process. 5.1 Synthesis The synthesis tool takes high level VHDL code and converts it to logic gates. During this step, any logic that isn t used will automatically be removed. The synthesis tool generates a set of netlists as its output Implementation Most of the optimizations happen during the Implementation phase. Implementation consists of three major steps: Translate, Map, and Place and Route. The Translation phase takes the output from the synthesis tool and converts it into a Xilinx Native Generic Database (NGD) file. There are no options to help optimize the design in this part, however the output NGD file can be opened by the Map tool. The map tool maps the logic stored in the NGD file and maps it to FPGA elements, such as Configurable Logic Blocks (CLBs) and Input/Output Buffers (IOBs). This is the phase where most of the optimization happens. A few of the most effective settings for performance could minimize combinational logic and optimize logic between blocks. This had a substantial impact on helping to meet timing constraints. The final output of the map tool is a Native Circuit Description (NCD) file. This file represents all existing components that will be placed in the FPGA. The final phase of implementation is the Place and Route tool. This tool takes in the NCD file as an input to determine where on the physical FPGA the different components will be placed and how the connections between these components will be routed. There are few optimizations to be performed in this stage, however, this stage is what will determine whether the design will meet the given timing requirements. 12 P a g e

13 Chapter 6 Testing and debugging To test our design, we used the tools listed in Chapter 4. We tested the downconverter as well as the components used in it. These tests were useful to make sure that each part works the way it is expected to work. The tests were incrementally made as we designed each new block. The method used to test blocks will be to put each block into a test bench, which will provide simulated inputs and make sure the expected outputs match. These simulations were run using ISim and the results were then loaded into MATLAB to verify they are correct. Whenever the results were incorrect we would begin to debug the issue. This involved looking through the waveforms to make sure the logic is being carried through as expected. When we found where there appeared to be a problem in the waveforms, we would search for the section of code that could have caused it. We then rerun the simulation and make sure the issue is solved. Chapter 7 Conclusions and Future Work To start this project, we created a digital downconverter from scratch to learn how the parts and tools function. This required designing a digital downconverter using VHDL, creating a test bench, and simulating the newly designed parts. Once we finished this, we started modifying the previously written code. We modified the DSP block to allow for the additional input. Additional testing will need to be done in both simulation and on hardware. There will also need to be additional work to make sure the design works with a larger amount of signal noise. Some future testing will require access to a ISE license to use the implementation tools on our FPGA. 13 P a g e

14 References [1] V. Chandrasekar, M. Schwaller, M. Vega, J. Carswell, K. V. Mishra, R. Meneghini and C. Nguyen, "SCIENTIFIC AND ENGINEERING OVERVIEW OF THE NASA DUAL-FREQUENCY DUALPOLARIZED," IGARSS, pp , [2] Pentek, "MODEL OPERATING MANUAL," [3] Texas Insturments, "16-Bit, 170/200-MSPS Analog-to-Digital Converters," [4] Xilinx, "LogiCORE IP DDS Compiler v4.0," [5] A. Devices, "Fundamentals of Direct Digital Synthesis (DDS)," [6] National Instruments, "Understanding Direct Digital Synthesis (DDS)," National Instruments, 4 May [Online]. Available: [Accessed 21 November 2016]. 14 P a g e

15 Appendix A: Abbreviations ADC - Analog to Digital Converters DAC - Digital to Analog Converters DDS - Direct Digital Synthesis DSP - Digital Signal Processing FPGA - Field Programmable Gate Array HDL - Hardware Description Language FIR - Finite Impulse Response GMP - Global Precipitation Measurement CLB - Configurable Logic Block IOBs - Input/Output Buffers Appendix B: Budget Currently no money has been spent on the project. One of the key parts of this project is that it will be done using existing hardware. Appendix C: Timeline Original timeline 10/27/2016 Finish going through the Gateflow IP_cores modules/parts. (modify and test modules) Meet with team to discuss functionality and issues with modules. 11/17/2016 Go through overall design of the existing design. (import project to Vivado). Brian explains to team on required changes to current design. 12/08/2016 Finish updating FPGA design with modified modules/updated modules. Present issues and architectural constraints. Brian sends code to team to review and test. 1/31/2017 Based on feedback from team, make modifications to design. 3/03/2017 Fit new design into FPGA and meet timing in Vivado tools. [will be iterative process for the team] 3/31/2017 Complete testing new design. [Working with team to maximize performance] 4/13/2017 Finish report and presentation Present project at E-Days. 15 P a g e

16 Revised Timeline Date Phase Task Who 1/10/2916 Design 1/31/2016 3/3/2017 Simulation Testing Optimization Finish updating FPGA design with modified modules/updated modules. Present issues and architectural constraints. Check the updated FPGA design with initial testcases. Test the code with more rigirous tescases. Complete new comprehensive design testing. Incorporate the code with the exisiting software and firmware and check for resource utilization and compatibility. If the above method fails use advanced features of the tools. Fit new design into FPGA and meet timing in ISE. Brian Brian, Mohit and Shashank Brian, Mohit and Shashank Brian Brian, Mohit and Shashank Brian, Mohit and Shashank Brian Brian, Mohit Present hardware preliminary testcases. Hardware testing and Shashank 3/31/2016 Complete testing new design. Brian Acknowledgments I would like to thank my project advisor Dr. V. Chandrasekar as well as Mohit Kumar and Shashank Joshil for being my graduate project mentors. I would also like to thank Nabeel Moin for his help understanding signal processing as well as debugging issues. 16 P a g e