Nan Ya NT5DS32M8AT-7K 256M DDR SDRAM
|
|
- Jeffry Francis
- 5 years ago
- Views:
Transcription
1 Nan Ya NT5DS32M8AT-7K 256M DDR SDRAM Circuit Analysis 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: Fax:
2 Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Some of the information in this report may be covered by patents, mask and/or copyright protection. This report should not be taken as an inducement to infringe on these rights Chipworks Incorporated This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization's corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. 5936LS CAR Revision 1.0 Published: October 11, 2002 Revision 2.0 Published: December 2, 2002 Revision 3.0 Published: October 17, 2003 Revision 4.0 Published: January 8, 2004 Revision 5.0 Published: June 22, 2004 Revision 6.0 Published: November 9, 2004
3 Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Table of Contents Introduction... Page 1 List of Figures... Page 2 Device Summary Sheet... Page 17 Top Level Diagram... Tab 1 Data Path... Tab 2 Address Path... Tab 3 Clocks... Tab 4 Voltage Generators... Tab 5 Row Redundancy... Tab 6 Column Redundancy... Tab 7 Test Modes... Tab 8 Mode Register... Tab 9 Self Refresh... Tab 10 Signal Naming Conventions and Symbol Definitions... Tab 11 Signal Cross-Reference List... Tab 12 About Chipworks... Tab 13
4 Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page 2 List of Figures Package Markings Package X-Ray Pin Configuration Die Markings Die Photograph Annotated Die Photograph Die Architecture MUX1 Definition MUX2 Definition MUX3 Definition Level Shifted NAND Definition Latency Counter Flip Flop Comparator Cell Definition D Flip-Flop 1 Definition D Flip-Flop 2 Definition D Flip-Flop 3 Definition D Flip-Flop 1A Definition D Flip-Flop 1B Definition D Flip-Flop 1C Definition D Flip-Flop 2A Definition D Flip-Flop 3A Definition D Flip-Flop 3B Definition D Flip-Flop 4A Definition D Flip-Flop 4B Definition D Flip-Flop 4C Definition D Flip-Flop 5 Definition XOR and XNOR Definitions Burst Cell Definition DBSA & Write Driver Architecture Block Decoding Address Bitmap Local Data Bus Access (for one bank) Rev /15/03 9:25 AM
5 Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page Top Level Diagram Data Path Memory Access Cells and Bitline Sense Amplifiers Data Bus Access Data Bus Write Drivers Data Bus Sense Amplifiers Write Data Line Drivers Data Output Switches Data Output Switches Data Output Switches Data Output Switches Data Output Switches Data Input Data Input Buffer Data Input Latch Data Input Steering Data Input Switches Data Input Switches Data Input Switches Read Data Line Drivers Data Output Register Data Output Buffer Multibit Test Multibit Test Comparator Multibit Test Comparator Multibit Test Comparator Multibit Test Comparator 4
6 Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page Multibit Test Output Address Path Address Input Address Buffers Bank Address Buffers Address Multiplexer Bank Address Latch Row Address Path Row Address Latches Block Select Block Predecoders Block Decoder X-Block Latches Load Unlink Generator Sense Clock Drivers Bitline Precharge Generator Row Decoders Row Predecoders Row Predecoders Row Factor Predecoder Row Factor Decoder Wordline Drivers Master Row Decoders Master Row Decoders Master Row Decoders Column Address Path Column Address Delay Line Column Address Counter/Latch Sequential Column Addresses (A1 & A2)
7 Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page Interleaved Column Addresses (A1 & A2) Column Addresses (A0 & A9) Column Addresses (A3 to A8) Column Address Latch (A9 & A11) Column Address Counter Clocks Column Address Counter Control Column Address Counter Counter Cell Column Address Latches Address Inverters Secondary Column Predecoders Secondary Column Predecoders Primary Column Predecoders Primary Column Predecoders Column Decoders Data Address Path Data Path Decoders Data Output Switches Control Data Output Switches Control Data Output Switch Register Refresh Counter Refresh Counter Cell Refresh Counter Multiplexer Clocks Control Input Buffers {RAS~} Buffer RAS/~ Buffer {CAS~} Buffer CAS/~ Buffer
8 Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page {WE~} Buffer WE/~ Buffer {CS~} Buffer CS/~ Buffer Chip Select Delay {CKE~} Buffer CKE Register BUFEN~ Generator Data Mask Input {DM*} Buffer {N/C} Buffer DM* Register DM* Register Clocks Data Mask Latches Internal Clock Generator {CK/CK~} Buffer {CK} Buffer {CK} Buffer Clock Generator Clock Generator Clock Generator Clock Generator Clock Generator Clock Buffer Control Clock Generator Enable Delay Decoder Clock Delay Cell Command Decoders Command Decoder Command Decoder 2
9 Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page Active Cycle Control Bank Activate Row Address Load Active Cycle Monitor ALLIDLE~ Block Predecoder Precharge Row Clocks Row Clocks Row Clocks Row Clocks Master Row Decoder Disable Master & Row Factor Precharge Block Decoder Selector Column Clocks Bank Selection Bank Selection Register Column Address Clock Generator YCLKs Generator Column Predecoder Enable Data Mask Multiplexer Write Mask Enable Read Mask Enable Read/Write Mask DBSA & Write Driver Enable Column Address Counter Burst Clock Bank Clocks Bank Clocks Bank Clocks Bank Clocks Bank Clocks 4
10 Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page Bank Clocks Bank Clocks Bank Clocks Bank Clocks Bank Clocks Burst and Read/Write Clocks Read/Write Clocks Write Latch Read/Write Pulse Generator Write Clock Generator Burst Length Counter Pipeline Clocks Latency Counter Latency Counter Latency Counter Pulse Generator Latency Counter Clock Input Pipeline Clocks Bank Activate Selection Data Output Clock Enable Data Output Clock Selection Data Input Steering Selection Pipeline Clocks Precharge Control Precharge Control Precharge Control Counter Read/Write Clocks Reset Data Path Clock Generator Data Path Control
11 Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page Data Path Clocks Data Output Switch Enable Write Data Line Driver Enable Read Data Line Driver Enable Register Pulse Generator Output Register Clocks Data Output Register Clocks Control Data Output Path Control Sequencer Sequencer Data Output Clock Selection DLL Top Level DLL Clock Inputs DLL Clock Multiplexer Clock Multiplexer DLL Delay Lines Reset Pulse Generator Delay Line Programmable Delay Lines Delay Lines Phase Comparator Delay Line Registers Delay Line Decoder Variable Clock Delay Tapped Delay Line DLL Multiplexer Control Clock 32-to-1 Multiplexer to-1 Multiplexer Output DLL Counters
12 Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page Counter Counter Counter Counter DLL Sequencer Sequencer Cell Sequencer Stage DLL Control Circuits DLL Set/Reset Generator DLL Control Signals DLL Control Signals {DQS} Buffers {DQS} Input Buffer DQS Clock Generator DQS Output Buffer Control {DQS} Output Buffer {DQS} Buffer Current Source Voltage Generators VBB Generator VBB Detector VBB Oscillators VBB Pump Internal VCC Generator Internal VCC Regulator Internal VCC Regulator Internal VCC Regulator Internal VCC Regulator Internal VCC Control Sense Voltage Generator
13 Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page VSP Bias Generator Sense Voltage Driver Sense Voltage Regulator Sense Voltage Control VBLP & VCP Generators VBLP Generator VCP Generator VPP Generator VPP Oscillator VPP Oscillator VPP Pump VPP Power-Up Pump VPP Reference Generator VPP Level Detector VPP Level Detector VPP Level Detector VPP Detector Enable Voltage Reference Sources Bandgap Reference Generator Mask Programmable Resistors Programmable Current Source Programmable Resistor Programmable Reference Generator Reference Generator Voltage Reference Select Voltage Multiplexer Unused Reference Generator Power-Up Circuitry Power-Up Circuit Power-Up Circuit 2
14 Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page Power-Up Sequencer Redundancy Power-Up Redundancy Sequencer Power-Up Level Shifter LH3 Local Supply Generator LH3 Local Supply Regulator Programmable Reference Voltage Voltage Test Voltage Divider Voltage Test Multiplexer Level Shifter Decoupling Circuitry Mid-Point Control Row Redundancy Row Redundancy Block Row Redundancy Programming Master Fuse Latch Address Fuse Latch Selector Master Row Decoder Enable Redundant Master Row Decoder Redundant Wordline Drivers Redundancy Test Option FUSEN~ Generator Data Line Access Column Redundancy Fuse Redundancy Block Fuse Programming
15 Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page Fuse Programming Latches Column Redundancy Programming Cell Programming/Address Comparator Redundancy Programming Column Redundancy Predecoders Column Redundancy Predecoders Redundant Column Access Column Redundancy Bank Select Column Redundancy Control Column Redundancy Control Test Latch Test Modes Test Mode Decoders Test Registers Test Mode Predecoders Test Mode Registers Test Mode Register Control Test Mode Reset Programmable Fuses Programmable Fuses Programmable Fuses Programmable Fuse Control Programmable Fuse Control Circuit Test Mode Address Decoder Test Latch Addresses Test Registers Test Mode Register Test Mode Register Test Mode Register 3
16 Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page Test Mode Register Test Mode Register Test Mode Register Test Mode Register Test Mode Register Test Mode Register Test Mode Switch Test Mode Controls Test Mode Register Test Mode Registers Second Stage Test Registers Test Mode Registers Test Mode Decoders Test Mode Register Test Mode Latches Test Mode Control Test Sequencer Flip Flop Test Mode Counter Counter Counter Control Counter Latch VDD Test Mode Signature Circuit Refresh Counter Test Mode Register Mode Register Set Decoder Mode Register Set Extended Mode Register Set
17 Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page Mode Register Mode Register Cells Mode Register Cells Burst Length Decoder Latency Decoder Extended Mode Register Extended Mode Register Cells Extended Mode Register Cells Extended Mode Register Inverters Extended Mode Decoder Enable Extended Mode Register Decoder DLL Enable Test Clock Generator Self Refresh Refresh Control Self Refresh Control Self Refresh Control Self Refresh Oscillator Refresh Oscillator Latch Self Refresh Timer Self Refresh Timer Cell Refresh Pulse Generator Refresh Counter Enable A.1.0 Symbol Conventions 1 A.1.1 Symbol Conventions 2 A.2.0 Symbol Definitions 1 A.2.1 Symbol Definitions 2 A.2.2 Symbol Definitions 3 A.2.3 Symbol Definitions 4
18 Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page 16 A.2.4 Symbol Definitions 5 A.2.5 Symbol Definitions 6 A.2.6 Symbol Definitions 7 A.3.0 Logic Gate Size Notation A.4.0 Transistor Size Notation A.5.0 Capacitor Size Notation
19 Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at Chipworks 1891 Robertson Road, Suite 500 Ottawa, Ontario K2H 5B7 Canada T F Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com
Infineon HYB18T512160AF-3.7 DDR2 SDRAM Circuit Analysis
March 13, 2006 Infineon HYB18T512160AF-3.7 DDR2 SDRAM Circuit Analysis For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology,
More informationNXP t505f Smart Card RFID Die Embedded NOR Flash Die From Smart Card World MIFARE Ultralight C
NXP t505f Smart Card RFID Die Die From Smart Card World MIFARE Ultralight C Custom Process Analysis For comments, questions, or more information about this report, or for any additional technical needs
More informationMediaTek MSD95C0H DTV SoC
MediaTek MSD95C0H Basic Functional Analysis 1891 Robertson Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613-829-0414 www.chipworks.com Basic Functional Analysis 2 Some of the information in this report
More informationOV µm Pixel Size Back Side Illuminated (BSI) 5 Megapixel CMOS Image Sensor
OmniVision OV5642 1.4 µm Pixel Size Back Side Illuminated (BSI) 5 Megapixel CMOS Image Sensor Circuit Analysis of the Pixel Array, Row Control, Column Readout, Analog Front End, and Pipelined A/D Converter
More informationSamsung VTU11A0 Timing Controller
Samsung VTU11A0 1891 Robertson Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613-829-0414 chipworks.com Some of the information in this report may be covered by patents, mask and/or copyright protection.
More informationTexas Instruments OMAP1510CGZG2 Dual-Core Processor Partial Circuit Analysis
October 11, 2005 Texas Instruments OMAP1510CGZG2 Dual-Core Processor Partial Circuit Analysis Table of Contents Introduction...Page 1 List of Figures...Page 4 Device Summary Sheet...Page 7 Schematics...
More informationFreescale SPC5604BF1CLL6 Embedded NOR Flash with M27V Die Markings 32 Bit Power Architecture Automotive Microcontroller 90 nm Logic Process
Freescale SPC5604BF1CLL6 Embedded NOR Flash with M27V Die Markings 32 Bit Power Architecture Automotive Microcontroller 90 nm Logic Process Process Review 3685 Richmond Road, Suite 500, Ottawa, ON K2H
More informationTexas Instruments TNETE2201 Ethernet Transceiver Circuit Analysis
October 31, 2003 Texas Instruments TNETE2201 Ethernet Transceiver Circuit Analysis Table of Contents List of Figures...Page 1 Introduction...Page 4 Device Summary Sheet...Page 6 Top Level Diagram...Tab
More informationSTMicroelectronics LSM330DLC inemo Inertial Module: 3D Accelerometer and 3D Gyroscope. MEMS Package Analysis
STMicroelectronics LSM330DLC inemo Inertial Module: 3D Accelerometer and 3D Gyroscope MEMS Package Analysis STMicroelectronics LSM330DLC 3D Accelerometer and 3D Gyroscope 2 Some of the information in this
More informationSTMicroelectronics L6262S BCD-MOS IC Structural Analysis
April 2, 2004 STMicroelectronics L6262S BCD-MOS IC Structural Analysis For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology,
More informationSTMicroelectronics S550B1A CMOS Image Sensor Imager Process Report
October 13, 2006 STMicroelectronics S550B1A CMOS Image Sensor Imager Process Report For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor
More informationSTMicroelectronics NAND128W3A2BN6E 128 Mbit NAND Flash Memory Structural Analysis
July 6, 2006 STMicroelectronics NAND128W3A2BN6E Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology,
More informationMagnaChip HV7161SP 1.3 Megapixel CMOS Image Sensor Process Review
September 21, 2005 MagnaChip HV7161SP 1.3 Megapixel Process Review For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology,
More informationLucent ORCA OR2C15A-2S208 FPGA Circuit Analysis
August 12, 1999 Lucent ORCA OR2C15A-2S208 FPGA Circuit Analysis Table of Contents List of Figures...Page 1 Device Summary Sheet...Page 4 Introduction...Page 6 PLC Architecture...Tab 1 Programmable Function
More informationLayout Analysis Analog Block
Layout Analysis Analog Block Sample Report Analysis from an HD Video/Audio SoC For any additional technical needs concerning semiconductor and electronics technology, please call Sales at Chipworks. 3685
More informationCombinational vs Sequential
Combinational vs Sequential inputs X Combinational Circuits outputs Z A combinational circuit: At any time, outputs depends only on inputs Changing inputs changes outputs No regard for previous inputs
More informationHardware Design I Chap. 5 Memory elements
Hardware Design I Chap. 5 Memory elements E-mail: shimada@is.naist.jp Why memory is required? To hold data which will be processed with designed hardware (for storage) Main memory, cache, register, and
More information16 Stage Bi-Directional LED Sequencer
16 Stage Bi-Directional LED Sequencer The bi-directional sequencer uses a 4 bit binary up/down counter (CD4516) and two "1 of 8 line decoders" (74HC138 or 74HCT138) to generate the popular "Night Rider"
More informationVLSI Design: 3) Explain the various MOSFET Capacitances & their significance. 4) Draw a CMOS Inverter. Explain its transfer characteristics
1) Explain why & how a MOSFET works VLSI Design: 2) Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel
More informationChapter 18. DRAM Circuitry Discussion. Block Diagram Description. DRAM Circuitry 113
DRAM Circuitry 113 Chapter 18 DRAM Circuitry 18-1. Discussion In this chapter we describe and build the actual DRAM circuits in our SK68K computer. Since we have already discussed the general principles
More informationIntroduction to CMOS VLSI Design (E158) Lecture 11: Decoders and Delay Estimation
Harris Introduction to CMOS VLSI Design (E158) Lecture 11: Decoders and Delay Estimation David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University
More informationChapter Contents. Appendix A: Digital Logic. Some Definitions
A- Appendix A - Digital Logic A-2 Appendix A - Digital Logic Chapter Contents Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic A. Introduction A.2 Combinational
More informationCSE 352 Laboratory Assignment 3
CSE 352 Laboratory Assignment 3 Introduction to Registers The objective of this lab is to introduce you to edge-trigged D-type flip-flops as well as linear feedback shift registers. Chapter 3 of the Harris&Harris
More informationLogic Design II (17.342) Spring Lecture Outline
Logic Design II (17.342) Spring 2012 Lecture Outline Class # 03 February 09, 2012 Dohn Bowden 1 Today s Lecture Registers and Counters Chapter 12 2 Course Admin 3 Administrative Admin for tonight Syllabus
More informationComputer Systems Architecture
Computer Systems Architecture Fundamentals Of Digital Logic 1 Our Goal Understand Fundamentals and basics Concepts How computers work at the lowest level Avoid whenever possible Complexity Implementation
More informationChapter 2. Digital Circuits
Chapter 2. Digital Circuits Logic gates Flip-flops FF registers IC registers Data bus Encoders/Decoders Multiplexers Troubleshooting digital circuits Most contents of this chapter were covered in 88-217
More informationPrinciples of Computer Architecture. Appendix A: Digital Logic
A-1 Appendix A - Digital Logic Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic A-2 Appendix A - Digital Logic Chapter Contents A.1 Introduction A.2 Combinational
More informationDIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES
DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES 1 Learning Objectives 1. Explain the function of a multiplexer. Implement a multiplexer using gates. 2. Explain the
More informationA MISSILE INSTRUMENTATION ENCODER
A MISSILE INSTRUMENTATION ENCODER Item Type text; Proceedings Authors CONN, RAYMOND; BREEDLOVE, PHILLIP Publisher International Foundation for Telemetering Journal International Telemetering Conference
More informationROM MEMORY AND DECODERS
ROM MEMORY AND DECODERS INEL427 - Spring 22 RANDOM ACCESS MEMORY Random Access Memory (RAM) read and write memory volatile Static RAM (SRAM) store information as long as power is applied will not lose
More information(CSC-3501) Lecture 7 (07 Feb 2008) Seung-Jong Park (Jay) CSC S.J. Park. Announcement
Seung-Jong Park (Jay) http://www.csc.lsu.edu/~sjpark Computer Architecture (CSC-3501) Lecture 7 (07 Feb 2008) 1 Announcement 2 1 Combinational vs. Sequential Logic Combinational Logic Memoryless Outputs
More informationA FOUR GAIN READOUT INTEGRATED CIRCUIT : FRIC 96_1
A FOUR GAIN READOUT INTEGRATED CIRCUIT : FRIC 96_1 J. M. Bussat 1, G. Bohner 1, O. Rossetto 2, D. Dzahini 2, J. Lecoq 1, J. Pouxe 2, J. Colas 1, (1) L. A. P. P. Annecy-le-vieux, France (2) I. S. N. Grenoble,
More informationCOMP2611: Computer Organization. Introduction to Digital Logic
1 COMP2611: Computer Organization Sequential Logic Time 2 Till now, we have essentially ignored the issue of time. We assume digital circuits: Perform their computations instantaneously Stateless: once
More informationHIGH PERFORMANCE MEMORY DESIGN TECHNIQUE FOR THE MC68000
MOTOROLA Semiconductor Products nc. AN-838 Application Note HGH PERFORMANCE MEMORY DESGN TECHNQUE FOR THE MC68000 This application note presents a technique for interfacing a 256K byte semi-transparent
More informationThe basic logic gates are the inverter (or NOT gate), the AND gate, the OR gate and the exclusive-or gate (XOR). If you put an inverter in front of
1 The basic logic gates are the inverter (or NOT gate), the AND gate, the OR gate and the exclusive-or gate (XOR). If you put an inverter in front of the AND gate, you get the NAND gate etc. 2 One of the
More informationpsasic Timing Generator
psasic Timing Generator Fukun Tang psasic Design Review July 1-2 2009 University of Chicago 1 Diagram of 40Gs/s Sampling Chip CLOCK (80MHz) IN(1:32) Timing Generator with 2 DLLs interleaved PD CP LF φ1
More informationFirst Name Last Name November 10, 2009 CS-343 Exam 2
CS-343 Exam 2 Instructions: For multiple choice questions, circle the letter of the one best choice unless the question explicitly states that it might have multiple correct answers. There is no penalty
More informationDigital Circuits 4: Sequential Circuits
Digital Circuits 4: Sequential Circuits Created by Dave Astels Last updated on 2018-04-20 07:42:42 PM UTC Guide Contents Guide Contents Overview Sequential Circuits Onward Flip-Flops R-S Flip Flop Level
More informationTesting Digital Systems II
Testing Digital Systems II Lecture 2: Design for Testability (I) structor: M. Tahoori Copyright 2010, M. Tahoori TDS II: Lecture 2 1 History During early years, design and test were separate The final
More informationLogic Gates, Timers, Flip-Flops & Counters. Subhasish Chandra Assistant Professor Department of Physics Institute of Forensic Science, Nagpur
Logic Gates, Timers, Flip-Flops & Counters Subhasish Chandra Assistant Professor Department of Physics Institute of Forensic Science, Nagpur Logic Gates Transistor NOT Gate Let I C be the collector current.
More informationLogic Devices for Interfacing, The 8085 MPU Lecture 4
Logic Devices for Interfacing, The 8085 MPU Lecture 4 1 Logic Devices for Interfacing Tri-State devices Buffer Bidirectional Buffer Decoder Encoder D Flip Flop :Latch and Clocked 2 Tri-state Logic Outputs
More informationIntroduction. NAND Gate Latch. Digital Logic Design 1 FLIP-FLOP. Digital Logic Design 1
2007 Introduction BK TP.HCM FLIP-FLOP So far we have seen Combinational Logic The output(s) depends only on the current values of the input variables Here we will look at Sequential Logic circuits The
More informationDIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) LATCHES and FLIP-FLOPS
COURSE / CODE DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) LATCHES and FLIP-FLOPS In the same way that logic gates are the building blocks of combinatorial circuits, latches
More informationMicroprocessor Design
Microprocessor Design Principles and Practices With VHDL Enoch O. Hwang Brooks / Cole 2004 To my wife and children Windy, Jonathan and Michelle Contents 1. Designing a Microprocessor... 2 1.1 Overview
More informationSequential Logic and Clocked Circuits
Sequential Logic and Clocked Circuits Clock or Timing Device Input Variables State or Memory Element Combinational Logic Elements From combinational logic, we move on to sequential logic. Sequential logic
More informationComputer Architecture and Organization
A-1 Appendix A - Digital Logic Computer Architecture and Organization Miles Murdocca and Vincent Heuring Appendix A Digital Logic A-2 Appendix A - Digital Logic Chapter Contents A.1 Introduction A.2 Combinational
More information55:131 Introduction to VLSI Design Project #1 -- Fall 2009 Counter built from NAND gates, timing Due Date: Friday October 9, 2009.
55:131 Introduction to VLSI Design Project #1 -- Fall 2009 Counter built from NAND gates, timing Due Date: Friday October 9, 2009 Introduction In this project we will create a transistor-level model of
More informationCSE115: Digital Design Lecture 23: Latches & Flip-Flops
Faculty of Engineering CSE115: Digital Design Lecture 23: Latches & Flip-Flops Sections 7.1-7.2 Suggested Reading A Generic Digital Processor Building Blocks for Digital Architectures INPUT - OUTPUT Interconnect:
More informationTiming Pulses. Important element of laboratory electronics. Pulses can control logical sequences with precise timing.
Timing Pulses Important element of laboratory electronics Pulses can control logical sequences with precise timing. If your detector sees a charged particle or a photon, you might want to signal a clock
More informationIT T35 Digital system desigm y - ii /s - iii
UNIT - III Sequential Logic I Sequential circuits: latches flip flops analysis of clocked sequential circuits state reduction and assignments Registers and Counters: Registers shift registers ripple counters
More informationFactory configured macros for the user logic
Factory configured macros for the user logic Document ID: VERSION 1.0 Budapest, November 2011. User s manual version information Version Date Modification Compiled by Version 1.0 11.11.2011. First edition
More information11. Sequential Elements
11. Sequential Elements Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 October 11, 2017 ECE Department, University of Texas at Austin
More informationECE 372 Microcontroller Design
E.g. Port A, Port B Used to interface with many devices Switches LEDs LCD Keypads Relays Stepper Motors Interface with digital IO requires us to connect the devices correctly and write code to interface
More informationMUHAMMAD NAEEM LATIF MCS 3 RD SEMESTER KHANEWAL
1. A stage in a shift register consists of (a) a latch (b) a flip-flop (c) a byte of storage (d) from bits of storage 2. To serially shift a byte of data into a shift register, there must be (a) one click
More informationPHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops
PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops Objective Construct a two-bit binary decoder. Study multiplexers (MUX) and demultiplexers (DEMUX). Construct an RS flip-flop from discrete gates.
More informationRensselaer Polytechnic Institute Computer Hardware Design ECSE Report. Lab Three Xilinx Richards Controller and Logic Analyzer Laboratory
RPI Rensselaer Polytechnic Institute Computer Hardware Design ECSE 4770 Report Lab Three Xilinx Richards Controller and Logic Analyzer Laboratory Name: Walter Dearing Group: Brad Stephenson David Bang
More informationSEQUENTIAL CIRCUITS THE RELAY CIRCUIT
SEQUENTIAL CIRCUITS THE RELAY CIRCUIT This circuit is one big circle. The main switch is open and the flexible contact is closed. Note: A closed inverter (NOT gate) circuit performs the same function.
More informationChapter 7 Memory and Programmable Logic
EEA091 - Digital Logic 數位邏輯 Chapter 7 Memory and Programmable Logic 吳俊興國立高雄大學資訊工程學系 2006 Chapter 7 Memory and Programmable Logic 7-1 Introduction 7-2 Random-Access Memory 7-3 Memory Decoding 7-4 Error
More informationME 515 Mechatronics. Introduction to Digital Electronics
ME 55 Mechatronics /5/26 ME 55 Mechatronics Digital Electronics Asanga Ratnaweera Department of Faculty of Engineering University of Peradeniya Tel: 8239 (3627) Email: asangar@pdn.ac.lk Introduction to
More informationAnalogue Versus Digital [5 M]
Q.1 a. Analogue Versus Digital [5 M] There are two basic ways of representing the numerical values of the various physical quantities with which we constantly deal in our day-to-day lives. One of the ways,
More informationAdvanced Devices. Registers Counters Multiplexers Decoders Adders. CSC258 Lecture Slides Steve Engels, 2006 Slide 1 of 20
Advanced Devices Using a combination of gates and flip-flops, we can construct more sophisticated logical devices. These devices, while more complex, are still considered fundamental to basic logic design.
More informationTopic D-type Flip-flops. Draw a timing diagram to illustrate the significance of edge
Topic 1.3.2 -type Flip-flops. Learning Objectives: At the end of this topic you will be able to; raw a timing diagram to illustrate the significance of edge triggering; raw a timing diagram to illustrate
More informationUniversity of Victoria. Department of Electrical and Computer Engineering. CENG 290 Digital Design I Lab Manual
University of Victoria Department of Electrical and Computer Engineering CENG 290 Digital Design I Lab Manual INDEX Introduction to the labs Lab1: Digital Instrumentation Lab2: Basic Digital Components
More informationMODULE 3. Combinational & Sequential logic
MODULE 3 Combinational & Sequential logic Combinational Logic Introduction Logic circuit may be classified into two categories. Combinational logic circuits 2. Sequential logic circuits A combinational
More informationCS 152 Computer Architecture and Engineering
CS 152 Computer Architecture and Engineering Lecture 12 Memory and Interfaces 2006-10-10 John Lazzaro (www.cs.berkeley.edu/~lazzaro) TAs: Udam Saini and Jue Sun www-inst.eecs.berkeley.edu/~cs152/ Last
More informationReport on 4-bit Counter design Report- 1, 2. Report on D- Flipflop. Course project for ECE533
Report on 4-bit Counter design Report- 1, 2. Report on D- Flipflop Course project for ECE533 I. Objective: REPORT-I The objective of this project is to design a 4-bit counter and implement it into a chip
More informationCopyright 2011 by Enoch Hwang, Ph.D. and Global Specialties. All rights reserved. Printed in Taiwan.
Copyright 2011 by Enoch Hwang, Ph.D. and Global Specialties All rights reserved. Printed in Taiwan. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form
More informationEECS 270 Midterm 2 Exam Closed book portion Fall 2014
EECS 270 Midterm 2 Exam Closed book portion Fall 2014 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: Page # Points
More informationCOSC 243. Sequential Logic. COSC 243 (Computer Architecture) Lecture 5 - Sequential Logic 1
COC 243 equential Logic COC 243 (Computer Architecture) Lecture 5 - equential Logic 1 Overview Last Lecture This Lecture equential logic circuits ource: Chapter 11 (10 th edition) Next Lecture Computer
More informationGated Driver Tree Based Power Optimized Multi-Bit Flip-Flops
International Journal of Emerging Engineering Research and Technology Volume 2, Issue 4, July 2014, PP 250-254 ISSN 2349-4395 (Print) & ISSN 2349-4409 (Online) Gated Driver Tree Based Power Optimized Multi-Bit
More informationReaction Game Kit MitchElectronics 2019
Reaction Game Kit MitchElectronics 2019 www.mitchelectronics.co.uk CONTENTS Schematic 3 How It Works 4 Materials 6 Construction 8 Important Information 9 Page 2 SCHEMATIC Page 3 SCHEMATIC EXPLANATION The
More informationDigital Circuits I and II Nov. 17, 1999
Physics 623 Digital Circuits I and II Nov. 17, 1999 Digital Circuits I 1 Purpose To introduce the basic principles of digital circuitry. To understand the small signal response of various gates and circuits
More informationIntroduction. Serial In - Serial Out Shift Registers (SISO)
Introduction Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a group of flip-flops connected in a chain so that the output from one flip-flop becomes
More informationDigital 1 Final Project Sequential Digital System - Slot Machine
Digital 1 Final Project Sequential Digital System - Slot Machine Joseph Messner Thomas Soistmann Alexander Dillman I. Introduction The purpose of this lab is to create a circuit that would represent the
More informationIMS B007 A transputer based graphics board
IMS B007 A transputer based graphics board INMOS Technical Note 12 Ray McConnell April 1987 72-TCH-012-01 You may not: 1. Modify the Materials or use them for any commercial purpose, or any public display,
More informationComputer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Sequential Circuits
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2007 opic Notes: Sequential Circuits Let s think about how life can be bad for a circuit. Edge Detection Consider this one: What is
More informationLED BASED SNAKE GAME
LED BASED SNAKE GAME Group 14 1 NAME ROLL NO MAJOR Muhammad Shoaib Hassan 14100005 Electrical Engineering Syed Muhammad Ali 14100167 Electrical Engineering Muhammad Ali Gulzar 14100017 Computer Science
More informationA Tour of PLDs. PLD ARCHITECTURES. [Prof.Ben-Avi]
[Prof.Ben-Avi]. (We shall now take a quick initial tour through the land of PLDs... the devices selected for this introductory tour have been chosen either because they are/were extremely popular or because
More informationIntroduction to Microprocessor & Digital Logic
ME262 Introduction to Microprocessor & Digital Logic (Sequential Logic) Summer 2 Sequential Logic Definition The output(s) of a sequential circuit depends d on the current and past states of the inputs,
More informationUNIT-3: SEQUENTIAL LOGIC CIRCUITS
UNIT-3: SEQUENTIAL LOGIC CIRCUITS STRUCTURE 3. Objectives 3. Introduction 3.2 Sequential Logic Circuits 3.2. NAND Latch 3.2.2 RS Flip-Flop 3.2.3 D Flip-Flop 3.2.4 JK Flip-Flop 3.2.5 Edge Triggered RS Flip-Flop
More information2.6 Reset Design Strategy
2.6 Reset esign Strategy Many design issues must be considered before choosing a reset strategy for an ASIC design, such as whether to use synchronous or asynchronous resets, will every flipflop receive
More informationPICOSECOND TIMING USING FAST ANALOG SAMPLING
PICOSECOND TIMING USING FAST ANALOG SAMPLING H. Frisch, J-F Genat, F. Tang, EFI Chicago, Tuesday 6 th Nov 2007 INTRODUCTION In the context of picosecond timing, analog detector pulse sampling in the 10
More informationFinal Exam review: chapter 4 and 5. Supplement 3 and 4
Final Exam review: chapter 4 and 5. Supplement 3 and 4 1. A new type of synchronous flip-flop has the following characteristic table. Find the corresponding excitation table with don t cares used as much
More information0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1 1 Stop bits. 11-bit Serial Data format
Applications of Shift Registers The major application of a shift register is to convert between parallel and serial data. Shift registers are also used as keyboard encoders. The two applications of the
More informationPESIT Bangalore South Campus
SOLUTIONS TO INTERNAL ASSESSMENT TEST 3 Date : 8/11/2016 Max Marks: 40 Subject & Code : Analog and Digital Electronics (15CS32) Section: III A and B Name of faculty: Deepti.C Time : 11:30 am-1:00 pm Note:
More informationChapter 3: Sequential Logic Systems
Chapter 3: Sequential Logic Systems 1. The S-R Latch Learning Objectives: At the end of this topic you should be able to: design a Set-Reset latch based on NAND gates; complete a sequential truth table
More informationInstructions. Final Exam CPSC/ELEN 680 December 12, Name: UIN:
Final Exam CPSC/ELEN 680 December 12, 2005 Name: UIN: Instructions This exam is closed book. Provide brief but complete answers to the following questions in the space provided, using figures as necessary.
More informationMUX AND FLIPFLOPS/LATCHES
MUX AN FLIPFLOPS/LATCHES BY: SURESH BALPANE Multiplexers 2:1 multiplexer chooses between two inputs S 1 0 Y 0 X 0 0 0 0 0 X 1 1 1 0 X 0 1 1 X 1 1 1 S Y @BALPANECircuits and Slide 2 Gate-Level Mux esign
More informationComputer Organization & Architecture Lecture #5
Computer Organization & Architecture Lecture #5 Shift Register A shift register is a register in which binary data can be stored and then shifted left or right when a shift signal is applied. Bits shifted
More informationDepartment of Electrical and Computer Engineering Mid-Term Examination Winter 2012
1 McGill University Faculty of Engineering ECSE-221B Introduction to Computer Engineering Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012 Examiner: Rola Harmouche Date:
More informationPhysics 323. Experiment # 10 - Digital Circuits
Physics 323 Experiment # 10 - Digital Circuits Purpose This is a brief introduction to digital (logic) circuits using both combinational and sequential logic. The basic building blocks will be the Transistor
More informationV6118 EM MICROELECTRONIC - MARIN SA. 2, 4 and 8 Mutiplex LCD Driver
EM MICROELECTRONIC - MARIN SA 2, 4 and 8 Mutiplex LCD Driver Description The is a universal low multiplex LCD driver. The version 2 drives two ways multiplex (two blackplanes) LCD, the version 4, four
More informationSEQUENTIAL LOGIC. Satish Chandra Assistant Professor Department of Physics P P N College, Kanpur
SEQUENTIAL LOGIC Satish Chandra Assistant Professor Department of Physics P P N College, Kanpur www.satish0402.weebly.com OSCILLATORS Oscillators is an amplifier which derives its input from output. Oscillators
More informationYEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING. EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall
YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall Objective: - Dealing with the operation of simple sequential devices. Learning invalid condition in
More informationMemory elements. Topics. Memory element terminology. Variations in memory elements. Clock terminology. Memory element parameters. clock.
Topics! Memory elements.! Basics of sequential machines. Memory elements! Stores a value as controlled by clock.! May have load signal, etc.! In CMOS, memory is created by:! capacitance (dynamic);! feedback
More informationL12: Reconfigurable Logic Architectures
L12: Reconfigurable Logic Architectures Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Frank Honore Prof. Randy Katz (Unified Microelectronics
More informationDigital Systems Laboratory 3 Counters & Registers Time 4 hours
Digital Systems Laboratory 3 Counters & Registers Time 4 hours Aim: To investigate the counters and registers constructed from flip-flops. Introduction: In the previous module, you have learnt D, S-R,
More information(Refer Slide Time: 1:45)
(Refer Slide Time: 1:45) Digital Circuits and Systems Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology, Madras Lecture - 30 Encoders and Decoders So in the last lecture
More informationEECS 270 Final Exam Spring 2012
EECS 270 Final Exam Spring 2012 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: Page # Points 2 /20 3 /12 4 /10 5 /15
More informationComputer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Sequential Circuits
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2009 opic Notes: Sequential Circuits Let s think about how life can be bad for a circuit. Edge Detection Consider this one: What is
More information