SERDES Eye/Backplane Demo for the LatticeECP3 Versa Evaluation Board User s Guide

Transcription

1 SERDES Eye/Backplane Demo for the LatticeECP3 Versa Evaluation Board User s Guide May 2011 UG44_01.1

2 Introduction This document provides technical information and instructions on using the LatticeECP3 SERDES Eye/Backplane Demo. The demo has been designed to demonstrate the performance of the LatticeECP3 SERDES I/O at Gbps. The document provides a circuit description as well as instructions for running the demo on the LatticeECP3 Versa Evaluation Board (See EB62, LatticeECP3 Versa Evaluation Board User s Guide). The LatticeECP3 Versa Evaluation Board is part of the LatticeECP3 Versa Development Kit. The demo walks you through the entire process in both Windows and Linux platforms. Please note that the operation in a Linux platform is limited to implementing the design process through bitstream generation only. In a Windows platform, further simulation and hardware evaluation of the demo can be accomplished. The SERDES Eye/Backplane Demo installs into the default location of C:\Lattice_DevKits\DK-ECP3-SERDES- 010\. However, you can install the demo files in a directory of your choice. The demo directory includes the following in Windows and root/dk-ecp3-serdes-010 in Linux: Verilog source code for the FPGA design Lattice Diamond implementation Project files and Aldec Active-HDL simulation script file Bitstream (in format of *.bit) ORCAstra plug-in GUI files specifically for this SERDES Eye/Backplane Demo Note: The ORCAstra plug-in is not available on the Linux platform This SERDES Eye/Backplane Demo User s Guide Hardware requirement for this loopback application test design: LatticeECP3 Versa Evaluation Board with LatticeECP3-35EA, 484-ball fpbga device 12V AC/DC power adapter (with international plug adapters) PC with ORCAstra (PC not provided) MHz on-board source for SERDES/PCS QUAD reference clock USB cable to download bitstream Backplane with SMAs (not provided) Pair of DC Blocks (not provided) Eye viewing instrument - DCA, DSO, etc. (not provided) SMA cables (not provided) Software application and driver requirements include: ispvm System software (version 18 or later) for FPGA bitstream download to the LatticeECP3 Versa Evaluation Board Lattice Diamond design software version 1.2 (or later) ORCAstra software for user control interface - Included with Diamond 1.2 (or later on Windows only) 2

3 SERDES Eye/Backplane Demo Design Overview A block diagram of the demo design is provided in Figure 1. Figure 1. SERDES Eye/Backplane Demo Design Error hdoutp/n_3 hdinp/n_3 LatticeECP3 PCS Quad (10-bit SERDES Mode) rx_half_clk_ch3 20 tx_half_clk_ch3 PRBS 2^7/2^31 Generator/Checker Design refclkp/n SCI 20 Status/ Control reset_n JTAG SCI ORCAstra SCI SCI Software Control sel_clk The basic concept of the design is a quad-based PRBS Generator/checker that transmits parallel data to a PCS quad. In turn, the PCS SERDES channels serialize the data in the transmit direction, and de-serialize it in the receive direction. The serial data stream can be: Looped back via a cable on the evaluation board, or Sent to a DCA or DSO for eye viewing. In both cases, a backplane of variable length can be included in the serial path. The PCS quad location PCSA is used for this SERDES Eye/Backplane demo. This is the only PCS Quad available with the ECP3-35EA device. The demo has been generated in 10-bit SERDES-only mode (20-bit data), at 3.2 Gbps per channel (actual demo rate is Gbps or equivalent). On the LatticeECP3 Versa Evaluation Board, only PCSA Channel 3 is available to the user via SMA connectors. Therefore, all demo procedures use Channel 3 of PCSA. Note that the reference design implements the LatticeECP3 PCS TX and RX Reset State machines described under the SERDES/PCS RESET section of TN1176, LatticeECP3 SERDES/PCS Usage Guide. Clock Sources PCS quad A is clocked by its designated differential clock input, refclkp/n. The reference clock frequency is MHz and has one source: the ispclock 5406A device (U13 on the LatticeECP3 Versa Evaluation Board). Internally to the PCS, the reference clock is multiplied by a factor of 20 to generate the Gbps per channel data rate. At the PCS/FPGA interface, a 20-bit data interface is used. This requires MHZ receive and transmit clocks. The PCS-generated rx_half_clk_ch3 and tx_half_clk_ch3 (see Figure 1) clock the PCS interface as well as the PRBS Generator/Checker RX and TX data. 3

4 PRBS Generator/Checker Quad There is one PRBS Generator/Checker quad block in the demo design. It is associated with PCS Quad A Channel 3. The PRBS generator/checker quad has the following characteristics: 20-bit wide data One PRBS Generator (2^7 and 2^31) One PRBS Checker (2^7 and 2^31) Control/Status interface to user registers. One Error Counter connected to a user register for monitoring. One real time Error signal indicator connected to an on-board LED. The ORCAstra block controls all user registers as well as the LatticeECP3 PCS QUAD via the SCI interface. ORCAstra is in turn controlled via the JTAG interface. See Figure 1. PRBS Generator/Checker Quad ORCAstra Console Window This demo utilizes a visual window plug-in to the base ORCAstra installation as shown in Figure 2. The LatticeECP3 FPGA PRBS Generator/Checker Console window is associated with logical LatticeECP3 PCS Quad 1 in the main ORCAstra software application as described later in this document. Figure 2. PRBS Generator/Checker Quad Console Window ERROR COUNTER: There is one ERROR COUNTER display corresponding to channel 3 in the PCSA Quad. When PRBS Channel 3 is Enabled, the error counter increments every time errors are detected at the PRBS checker. The counter is only eight bits wide so the maximum count reached is hff. When the counter reaches hff, it does not roll back to zero unless the Clear Error Counter button is selected. The counter will not increment unless the corresponding PRBS channel is enabled. Clear Error Counters: When the Clear Error Counter button is selected, it asynchronously clears the content of the PRBS checker error counter. 4

5 Inject Error button: The PRBS channel needs to be enabled for this error injection feature to work. The demo design injects a single incorrect parallel data word in the transmitted PRBS data every time a positive edge occurs on the register bit associated with the Inject Error button. So, an incorrect data word is inserted every time the Inject Error button is selected. When a channel is in a SERDES near-end (HDOUT->HDIN) loopback, a single incorrect data word injected by a channel generator does not always correspond to a single count increment in the checker error counter. The injected error can cause the error counter to increment by as much as three counts. This is attributed to the nature of the PRBS checker design. PRBS Selection button: This button allows the selection of either 2^7 or 2^31 PRBS generation and checking. PRBS CH DISABLED/ENABLED: This enables/disables both the transmission of PRBS data from the generator, and the detection of errors by the checkers of a quad. When this button is disabled, the PRBS ERROR counters in the visual window stop incrementing, and the real time output PRBS Error signal indicator remains low (see Figure 1 and Table 2). PRBS Generator/Checker User Registers Map The user-accessible registers for the PRBS generator/checker quad are defined in Table 1. All register addresses are in hexadecimal. Also note that register address h00800 (not shown in Table 1) is a read-only register that contains the version number of the design. Table 1. User Registers Map GUI Option PRBS SEL PRBS CH 3 Enabled/Disabled PRBS ERR CNT 08004, bits [0:7] PCSA FPGA Register Ch3 Description 08000, bit 0 0=2^7-1 1=2^31-1 0=disable 08000, bit 7 1=enable Count up to flip-flop. Clear on read. Inject Error 08000, bit 2 Write 0 then 1 to inject error. Clear Error Cntr 08000, bit 3 Write 0 to clear. LatticeECP3 Versa Evaluation Board Setup There are two evaluations that can be done using the SERDES Eye/Backplane Demo design. The first demo is to loop the PRBS data back to the LatticeECP3 and check the data. The second demo evaluates the CML eye diagram of the high-speed data signal to a DSO. These setups assume the following. 1. ispvm System software is installed on a PC. The ispvm installation executable is included with the Diamond design software. 2. ORCAstra is installed on a PC. The ORCAstra installation executable is included with the Diamond design software. 3. The board is connected to the PC using the USB cable supplied. The USB cable is connected to J2 on the board. 4. Power is applied to the board via the provided power supply. Figure 3 shows the board setup for Loopback test. 5

6 SERDES Eye/Backplane Demo for the LatticeECP3 Versa Evaluation Board Lattice Semiconductor Figure 3. LatticeECP3 Versa Evaluation Board Setup for Loopback Test SERDES Eye/Backplane Demo Design Signal Descriptions Table 2 lists all the SERDES Eye/Backplane Demo Design signals that are connected on the LatticeECP3 Versa Evaluation Board. Table 2. Signal Descriptions Signal Name Type reset_n I tck I tdi I tdo O tms I Error_3 Board Connection Description SW1 Push Button FPGA global active low reset To on-board JTAG logic JTAG pins O Red LED D27 lights when errors occur PRBS error indicator for channel 3. Will not light if PRBS channel is disabled in the ORCAstra PRBS Console window. hdinp_3/ hdinn_3 I SMA J5 and J6 Channel 3 differential high-speed SERDES inputs hdoutp_3/ hdoutn_3 O SMA J7 and J8 Channel 3 differential high-speed SERDES outputs Loading the LatticeECP3 SERDES Eye Demo Bitstream with ispvm Follow the instructions below to load the SERDES Eye demo bitstream. 1. Start ispvm System software by selecting Start >Programs >Lattice Diamond 1.2 >Accessories >ispvm System. For Linux, type ispvm in the command line. Please refer to the Lattice Diamond Installation Notice for proper setting of the Environment Variables. 2. In the ispvm window, select the green Scan button (see Figure 4). LFE3-35EA will appear in the device list. 6

7 3. If ispvm does not detect the board or the device, select Options >Cable and I/O Port Setup. The Cable and I/O Port Setup window opens. Select Auto Detect and select USB2. Select OK. Select the green Scan button again and ensure LFE3-35EA is in the device list. If the board is not detected in the Linux platform, refer to the ispvm System Linux Installation and Setup Manual (ispvmlinuxinstallation.pdf) in the ispvm System installation directory. 4. Double-click on LFE3-35EA in the device list. The Device Information window will appear. 5. Set Device Access Options to JTAG1532 Mode and Operation to Fast Program (default setting). 6. Set the Data File to <demo_directory>\bitstreams\serdes_eye_demo_impl1.bit and select OK. 7. Select Go in the ispvm window. ispvm will download the bitstream to the LatticeECP3 device. A successful download of the bitstream is indicated by a green icon and PASS in the Status column as shown in Figure 4. Figure 4. ispvm Setup Running a Demo with the ORCAstra PCS View This section describes the use of ORCAstra to interactively change and monitor the LatticeECP3 PCS and useraccessible registers. This section is for the Windows platform only. Starting ORCAstra Ensure the LatticeECP3 Demo bitstream has been loaded, then: 7

8 1. Start the ORCAstra software by invoking ORCA-stra.exe from the ORCAstra directory (ex: C:\lscc\ diamond\1.2\orcastra\. The following ORCAstra FPGA Control Center window appears: 2. Select Interface > 1 ispvm JTAG Hub USB Interface. The system detects two Devices. Select A and select OK, as shown in Figure 5. Figure 5. Multiple Devices Window 3. You will see the window shown below. Select OK. 4. Select Device >4 Lattice ECP3. Also select Options and un-check Display Data in [7:0] Order in Data Box. 5. Select the ECP3 PCS1 button. The ECP3-PCS 1 window will appear. Select the Main tab, and select the Pwr, Rst, Alrms, and SerDes Buffer Options tabs. The resulting ECP3-PCS 1 window is shown in Figure 6. 8

9 Figure 6. Lattice PCS ORCAstra View 6. From the main ORCAstra Window, select CustomProgrammability-> Visual Window. 7. In the new window, select File->Open and navigate to select <demo_directory>\orcastra Plugins\EyeDemo.vis. You will see the PRBS Gen./Check Visual Window shown in Figure Make sure Continuous Polling is checked in the main ORCAstra window. This ensures that changes in the GUI are instantly reflected in the hardware registers. Configuring PCS 1 Options in ORCAstraECP3-PCS 1 Window Power, Reset and Alarms The default Pwr, Resets and Alarms section contains the following important information (See Figure 6): A single red or green LED indicates the status of the entire quad or all of the four channels of the quad. There are two LEDs, red and green for plol. If the green LED glows, it means a successful PLL lock. If the red LED glows, it means the PLL failed to lock. Be sure PLL is locked before continuing with the demo. The green and red LEDs (one per channel) indicate Receive CDR lock (rlol). Green indicates a successful lock. This view also allows the user to identify which channels (or the entire QUAD), are powered down or reset. This view also allows users to reset PCS digital logic (lane_tx_rst and lane_rx_rst), as well as SERDES logic (macro_rst) and the whole QUAD (quad_rst). For more details, refer to TN1176, LatticeECP3 SERDES/PCS Usage Guide. SERDES Buffer Options View This view allows controlling the characteristics of output, input, and reference clock buffers: TX pre-emphasis, TX amplitude, RX equalization, TX and RX buffer termination and coupling. These options can be changed by clicking the Channel 3 tab in the ECP3-PCS1 window. Refer to SERDES Buffer Options Section shown in Figure 6. 9

10 Typical Backplane Demo Applications As mentioned earlier, the serial data stream can be: Looped back via a cable on the evaluation board, or Sent to a DSO or DCA for eye viewing. This document describes using a DSO. The DCA requires an external trigger input. SERDES Eye/Backplane Demo on PCS Quad PCSA using DSO A typical DSO SERDES Eye/Backplane Demo application with PCS PCSB is illustrated in Figure 7. Figure 7. Typical DSO SERDES Backplane Eye Demo on PCS Quad PCSA To PC ispvm J12 J MHz MHZ Osc. PCSB_HDOUT* PCSA_HDOUT3 PCSB_HDIN* SW1 SW1 RESET SEL_CLK 12V REFCLK (PCSB) (PCSA) LatticeECP3 PCS Quad (10-Bit SERDES Mode) R LED2 (D24) MCA_RESYNC PART: LFE3-95E -7FN1152CES rx_half_clk_ch3 20 tx_half_clk_ch3 20 PRBS 2^7/2^31 Generator/Checker Design LED CH3 Checker Error Agilent DSO81304B Backplane DC BLOCKS The hardware setup is as follows: The LatticeECP3 Versa Evaluation Board has an on-board reference clock (ispclock5406a device) that applies differential clock inputs to the PCSA reference clock input. Connect the SMA cables from the channel 3 high speed outputs, J7 and J, to SMA terminals on the backplane. If you do not want to use a backplane, connect the SMA cables from J7 and J8 directly to the DC blocks on the DSO. Setup the Agilent DSO81304B instrument using the setup file: <demo_directory>\misc\ DSO81394B_setup.set In previous sections of this user s guide, you have already connected the power supply to the LatticeECP3 Versa Evaluation Board, loaded the LatticeECP3 SERDES Eye/Backplane demo bitstream to the board, invoked ORCAstra, and customized the ORCAstra interface with the PRBS Generator/Checker Console window and ECP3-PCS 1 windows on your computer. Perform the following steps to complete the demo: 1. In the ORCAstra FPGA Control Center window, be sure to check the Continuously Polling check box. 2. Press SW1 FPGA GSRN on the LatticeECP3 Versa Evaluation Board to re-acquire the ref clock. 10

11 3. In the Power, Resets, and Alarms tab of the ECP3-PCS 1 window, power down channels 0, 1 and 2 (uncheck tpwdnb and rpwdnb for channels 0, 1, and 2; Channel 3 must remain checked). 4. In the PRBS Generator/checker Console window, select 2^7 or 2^31 for the PRBS pattern. If you select 2^31, then also set Receive equalization to 11: Long-Reach Eq in the SERDES Buffer Option tab and Channel 3 tab, of the ECP3-PCS 1 window. 5. In the PRBS Generator/checker Console window, make sure PRBS channel 3 is enabled. As a result of running the demo steps, a PRBS eye should appear on the DSO screen. Figure 8 illustrates a Gbps differential eye based on 2^7 PRBS mode, the SERDES buffer settings, and the SERDES output SMAs J7 and J8 connected directly to the DC blocks (no backplane). In a typical backplane application, the SERDES Buffer Options of PCS1 in ORCAstra (Figure 6) allows real-time tweaking of output buffer characteristics, as different backplane lengths are utilized to maintain a clean SERDES eye diagram at the DSO input. The eye in Figure 8 can change if any of the TX buffer options, such as amplitude, pre-emphasis, and coupling, are changed. Figure 8. DSO Differential Eye Diagram with PCS Quad PCSA and No Backplane SERDES Eye/Backplane PRBS Loopback Demo In a typical PRBS backplane loopback application: The FPGA PRBS Generator is used to transmit data from the FPGA to the PCS TXD ports on a given channel. The PCS SERDES HDOUT pins are connected to a backplane through SMA cables. The other backplane terminals connect to the PCS HDIN channel inputs through SMA cables. Note: To do the loopback demo without a backplane, use the SMA cables to directly connect HDOUT to HDIN on the LatticeECP3 Versa Evaluation Board. The PCS RXD ports then feed the recovered data to the FPGA PRBS Quad Checker. 11

12 This type of application is illustrated in Figure 3. This setup applies to PCSA Quad, Channel 3 which has been brought out on the LatticeECP3 Versa Evaluation Board. This application can make use of the ORCAstra PRBS Generator/Checker Quad Console window from Figure 2 and the SERDES Buffer Options in the ORCAstra ECP3-PCS 1 window (see Figure 6). While looping PRBS data on channel 3 the PRBS Generator/checker Console window is used to verify error-free PRBS data is received, while the ECP3-PCS 1 window is used to tweak output and input buffer options (as different backplane lengths are used). The following steps describe how to run through a PRBS loopback demo on channel 3. The HDIN and HDOUT SMA (P, N) pairs are (J5 and J6) and (J7 and J8) respectively. 1. Make sure power is supplied to the LatticeECP3 Versa Evaluation Board. 2. Make sure HDOUT3 is looped back to HDIN3. Note: To do the loopback demo without a backplane, use the SMA cables to directly connect HDOUT to HDIN on the LatticeECP3 Versa Evaluation Board. 3. Press SW1 FPGA GSRN on the LatticeECP3 Versa Evaluation Board to re-acquire the reference clock. 4. Load the LatticeECP3 SERDES Demo bitstream as previously described. 5. Start an ORCAstra session and load the ECP3-PCS 1 window and the PRBS Generator/Checker Console window as previously described. 6. Make sure the Continuous Polling box is checked in the ORCAstra FPGA Control Center window. 7. In the Power, Resets, and Alarms tab of the ECP3-PCS 1 window, power down channels 0, 1 and 2 (uncheck tpwdnb and rpwdnb for channels 0, 1 and 2). 8. In the PRBS Generator/Checker Quad Visual Window: A. Select 2^7 or 2^31 for PATTERN. If you select 2^31, then also set Receive equalization to 11: Long- Reach Eq in the SERDES Buffer Option tab, channel 3, of the ECP3-PCS 1 window. 12

13 B. ENABLE channel 3. The generator and checker for channel 3 are now transmitting and checking PRBS packets. After this step, rlol should be solid green. Also verify that plol is solid green. If any of these indicators are red, then proceed to debugging these indicators as indicated in step 7D. C. Clear all counters by pressing the Clear Error Cntr button. D. If the ERR COUNTER for channel 3 increments and/or the D27 error LED lights up, then the PRBS checker is receiving patterns with errors. Note that the error counters will not rollover after reaching hff. It is necessary to reset the counter to ensure no new errors are received. E. Verify that the Power, Reset and Alarm section in the ECP3-PCS 1 window does not show any PLL loss of lock (plol) or CDR loss of lock (rlol). a. A red plol indicates that the reference clock source to the TX PLL is not stable or may have the incorrect frequency. b. A red rlol indicates incorrect activity on the HDIN* inputs. The input signals may be too attenuated by the medium. F. Modifying some of the input and output buffer settings in the SERDES Buffer Options section of ECP3- PCS 1 window. (ex: TX pre-emphasis, TX amplitude, RX equalization) to address the rlol issue. Implementing and Simulating the Reference Design The steps below explain how to run the SERDES Eye/Backplane Demo reference design source code through Diamond map, place and route, bitstream generation, and simulation. Simulation is supported in Windows only. Both implementation and simulation start with the same steps: 1. Open Lattice Diamond design software. 2. Open <demo_directory>\target\serdes_eye_demo.ldf. This will load the Verilog-based project, as shown in Figure 9. Figure 9. Diamond Verilog HDL Design 13

14 Implementation To implement the design and generate a bitstream, double-click Bitstream File in the Process window. This will run through the full synthesis, place and route flow and generate a new serdes_eye_demo_impl1.bit file in the impl1 folder. Simulation The simulation process uses the custom.do Aldec Active-HDL simulation script located under the Target directory. To ensure this script is used, follow the steps below, as illustrated in Figures 10 to 14: 1. Open the Lattice Diamond design tool. Select Tools->Simulation Wizard. Select Next and provide the name of your choice as the project name. Select Next. RTL should be selected. Select Next. 2. In the Add Source window click the + button and add the test bench file..serdes\sim\src\aaa_serdes_tb.v. Select Next and Finish. 3. The Active-HDL environment will open. Select Tool- >Execute Macro and select the custom.do file. 4. The script compiles all necessary design and test bench files and runs the simulation into the Aldec Waveform window shown in Figure 15. Figure 10. Configuring Aldec Simulation 14

15 Figure 11. Add Source Window Figure 12. Adding Test Bench 15

16 Figure 13. Summary of Sources Figure 14. Executing Custom.do File 16

17 Figure 15. Aldec Active-HDL Simulation References The following documents provide more information: TN1176, LatticeECP3 SERDES/PCS Usage Guide DS1021, LatticeECP3 Family Data Sheet EB62, LatticeECP3 Versa Evaluation Board User s Guide Technical Support Assistance Hotline: LATTICE (North America) (Outside North America) techsupport@latticesemi.com Internet: Revision History Date Version Change Summary April Initial release. May Updated steps for demos to include pressing of GSRN Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 17