PESIT Bangalore South Campus
|
|
- Elwin Goodwin
- 5 years ago
- Views:
Transcription
1 SOLUTIONS TO INTERNAL ASSESSMENT TEST 3 Date : 8/11/2016 Max Marks: 40 Subject & Code : Analog and Digital Electronics (15CS32) Section: III A and B Name of faculty: Deepti.C Time : 11:30 am-1:00 pm Note: Answer five complete questions each of 8 marks, one from each part PART a) Differentiate between ideal Op-Amp and practical Op-Amps. (4 Marks) Ideal OPAMP Practical OPAMP Infinite voltage gain Practical Voltage gain around 200,000 Infinite input impedance Practical input impedance about Ω for FET input op-amps Zero output impedance Low output impedance independent of load Infinite bandwidth Practically limited to few MHz range(slew rate limited to V/µs Linear irrespective of entire analog signal range Zero input offset voltage Mostly Linear with slight variation Practical very small value of input offset voltage b) Explain the working of Op-Amp as peak detector circuit. (4 Marks) PEAK DETECTOR measures the Positive peak values of the Square wave input. During the positive half-cycle of Vin, the output of the op amp drives D1 on, charging capacitor C to the positive peak value Vp of the input voltage Vin. Thus, when D1 is forward biased, the OP AMP operates as a voltage follower. On the other hand, during the negative half-cycle of Vin, diode D1 is reverse biased, and voltage across C is retained. The only discharge path for C is through R1 since the input bias current Ib is negligible For proper operation of the circuit, the charging time constant (CRdiode) and discharging time constant (CR1) must satisfy the following conditions: The capacitor C1 charges rapidly, via D1, to the peak positive value of an input signal, but discharges slowly via R1 when the signal falls below the peak value.
2 The second opamp is used as a voltage-following buffer stage; to ensure that R1 is not shunted by external loading effects.this circuit outputs the peak voltage of the input. The capacitor stores the current peak voltage. If the input voltage is larger, the op-amp output goes positive until the capacitor is charged up to the new peak value. If the input voltage is smaller, the diode keeps the capacitor from being discharged. 2. Explain with a neat connection diagram and waveforms how IC555 timer is used as an astable multivibrator (8 Marks) When Q is low or output V OUT is high, the discharging transistor is cut-off and the capacitor C begins charging toward V CC through resistances R A and R B. Because of this, the charging time constant is (R A + R B ) C. The charging of the capacitor will be done using two external resistors RA& RB. When the voltage of the capacitor goes above 2/3 Vcc, then the output of comparator1 will be High, which sets the flip-flop so that its Q is high and the timer output Q (output at pin no 3) is low. So the final o/p of the timer is LOW. High Q drives discharge transistor to saturation and the discharge transistor Q1 transistor switches ON. The capacitor starts discharging through resistor RB with a discharging time constant R B C. With the discharging of capacitor, trigger voltage at inverting input of comparator 2 decreases. When the capacitor voltage becomes less than 1/3 VCC, comparator 2 output goes high resetting the flip flop (Q=0, Q =1).This cycle repeats.
3 3. For the relaxation oscillator in Figure determine the peak to peak amplitude and frequency of the square wave output given that saturation output voltage of OPAMP is +/- 12.5V at power supply voltages of +/- 15V β = R1/(R1+R2) = PART2 (8 Marks) T = 2 RC ln [(1 + β)/(1- β)] = ms F=1/T=2.13 khz Peak to peak amplitude = 2Vsat = 25 V 4. The figure on the right shows as second order low pass filter built around a single operational amplifier. Calculate the values of R1,R2,C1,C2 and R3.The filter has a cutoff frequency of 10kHz,Q factor of and input impedance not less than 10 kω (8Marks) Let R1=R2= R =10 kω Q = 0.5 * C1/C2 For Q=0.707 C1= 2C2 Given fc= 1/(2πR C1C2) =10 khz Hence C2 = µf C1 = 2C2 = µf R3= R1+R2= 20 kω
4 PART 3 5. a) Explain the working of Schmitt Trigger along with its Transfer characteristic. (5 Marks) A Schmitt trigger is an electronic circuit that is used to detect whether a voltage has crossed over a given reference level. It has two stable states (Bistable Multivibrator). It is useful as a signal-conditioning device. Slow varying inputs are converted to a rectangular output that has sharp leading and trailing edges. The Schmitt trigger is a comparator application which switches the output negative when the input passes upward through a positive reference voltage. It then uses positive feedback of a negative voltage to prevent switching back to the other state until the input passes through a lower threshold voltage, thus stabilizing the switching against rapid triggering by noise as it passes the trigger point. That is, it provides feedback which is not reversed in phase, but in this case the signal that is being fed back is a negative signal and keeps the output driven to the negative supply voltage until the input drops below the lower design threshold. Transfer Characteristic The value of the input voltage Vi that causes the output to jump from LOW to HIGH is called the positive going threshold VT+. The value of Vi that causes the output to switch from HIGH to LOW is called the negative-going threshold VT-. The transfer characteristic is as shown below: b) Derive characterstic equation of SR Flip Flop. (3 marks) A description of the next state of a flip-flop. Characterstic equation is an expression for Qt+1 in terms of the present state and input.it can be constructed from the Karnaugh Map
5 6. With a neat logic diagram and truth table, explain the working of master slave JK Flip - Flop along with its implementation using NAND gates. (8 Marks) The J and K data is processed by the flip-flop after a complete clock pulse. On the positive transition of the clock, the data from the J and K inputs is transferred to the master. On the negative transition of the clock, the data from the master is transferred to the slave. The flip-flop is referred to as pulse-triggered. When J = K = 1, the output can continue to toggle as long as the clock is high. This condition is called the racearound condition. Propagation delay prevents the JK flip-flop from racing. The JK flip-flop output changes after the PT of the clock. The new Q and Q values are too late to coincide with the PTs driving the AND gate. If PTs are narrower than the propagation delay of the flip-flop, the returning Q and Q arrive too late to cause false triggering. A better method to avoid race around condition is to use a master-slave circuit
6 7. a) Write the Verilog code for a positive edge triggered JK Flip Flop (5 Marks) module JK_FF (J,K,CLK,Q,Qnot); output Q,Qnot; input J,K,CLK; reg Q; assign Qnot = ~ Q ; CLK) case({j,k}) 2'b00: Q = Q; 2'b01: Q = 1'b0; 2'b10: Q = 1'b1; 2'b11: Q = ~ Q; endcase endmodule b) Explain the characteristics of an ideal clock. (3 Marks) 1. Clock levels must be absolutely stable (HIGH = + 5V,LOW= 0V,unchanging) 2. Ideal clock has zero transition time 3. The frequency of the clock should be steady and unchanging over a period of time
7 8. With a neat logic and timing diagram, explain the working of a 4 - bit SISO register using JK Flip Flops The serial in/serial out shift register accepts data serially--that is, one bit at a time on a single line. It produces the stored information on its output also in serial form. With four stages, this register can store up to four bits of data; its-storage capacity is four bits. (8 Marks) JK FFs cascaded Q to J, Q to K with clocks in parallel to yield an alternate form of the shift register above. A serial-in/serial-out shift register has a clock input, a data input, and a data output from the last stage. In general, the other stage outputs are not available Otherwise, it would be a serial-in, parallel-out shift register.. The waveforms below are applicable to either one of the preceding two versions of the serial-in, serial-out shift register. The three pairs of arrows show that a three stage shift register temporarily stores 3-bits of data and delays it by three clock periods from input to output. At clock time t1 a data in of 0 is clocked from D to Q of all three stages. In particular, D of stage A sees a logic 0, which is clocked to QA where it remains until time t2. At clock time t2 a data in of 1 is clocked from D to QA. At stages B and C, a 0, fed from preceding stages is clocked to QB and QC. At clock time t3 a data in of 0 is clocked from D to QA. QA goes low and stays low for the remaining clocks due to data in being 0. QB goes high at t3 due to a 1 from the previous stage. QC is still low after t3 due to a low from the previous stage. QC finally goes high at clock t4 due to the high fed to D from the previous stage QB. All earlier stages have 0s shifted into them. And, after the next clock pulse at t5, all logic 1s will have been shifted out, replaced by 0s
8 9. With neat diagram, explain a 4 bit universal shift register (8 Marks) Universal Shift Register is a register which can be configured to load and/or retrieve the data in any mode (either serial or parallel) by shifting it either towards right or towards left. In other words, a combined design of unidirectional (either right- or left-shift of data bits as in case of SISO, SIPO, PISO, PIPO) and bidirectional shift register along with parallel load provision is referred to as universal shift register. Such a shift register capable of storing n input bits. n 4 1 multiplexers to drive the input pins of n flip-flops in the register which are also connected to clock and clear inputs. All of the multiplexers in the circuit share the same select lines, S1 and S0 (pink lines in the figure), in order to select the mode in which the shift registers operates. First input (Pin Number 0) connected to the output pin of the same flip-flop i.e. zeroth pin of MUX1 is connected to Q1; zeroth pin of MUX2 is connected to Q2, Zeroth pin of MUX n is connected to Qn. Second input (Pin Number 1) connected to the output of the very-previous flip-flop (except the first flip-flop FF1 where it acts like an serial-input to the input data bits which are to be shifted towards right) i.e. first pin of MUX2 is connected to Q1, first pin of MUX3 is connected to Q2, first pin of MUXn is connected to Qn-1.Third input (Pin Number 2) connected to the output of the very-next flip-flop (except the first flip-flop FFn where it acts like an serial-input to the input data bits which are to be shifted towards left) i.e. second pin of MUX1 is connected to Q2, second pin of MUX2 is connected to Q3, second pin of MUXn-1 is connected to Qn. Fourth input (Pin Number 3) connected to the individual bits of the input data word which is to be stored into the register, thus providing the facility for parallel loading.
9 10. a) Explain briefly serial adder to add two 4 - bit numbers with a neat sketch. (5Marks) Shift control used to stop addition, Generally not a good idea to gate the clock Shift register can be arbitrary length, Full Adder can be built from combinational logic b) Write Verilog HDL code for 4-bit SIPO shift register where all the flip-flop outputs are available externally. module sipo (d,clk,q); input clk,d; output [3:0]q; wire [3:0]q; always@(negedge clk) begin q[0] <= d; q[1] <= q[0]; q[2] <= q[1]; q[3] <= q[2]; end endmodule // Nonblocking assignment *********** (3Marks)
Unit-5 Sequential Circuits - 1
Unit-5 Sequential Circuits - 1 1. With the help of block diagram, explain the working of a JK Master-Slave flip flop. 2. Differentiate between combinational circuit and sequential circuit. 3. Explain Schmitt
More informationSEQUENTIAL LOGIC. Satish Chandra Assistant Professor Department of Physics P P N College, Kanpur
SEQUENTIAL LOGIC Satish Chandra Assistant Professor Department of Physics P P N College, Kanpur www.satish0402.weebly.com OSCILLATORS Oscillators is an amplifier which derives its input from output. Oscillators
More informationLogic Gates, Timers, Flip-Flops & Counters. Subhasish Chandra Assistant Professor Department of Physics Institute of Forensic Science, Nagpur
Logic Gates, Timers, Flip-Flops & Counters Subhasish Chandra Assistant Professor Department of Physics Institute of Forensic Science, Nagpur Logic Gates Transistor NOT Gate Let I C be the collector current.
More informationIntroduction. NAND Gate Latch. Digital Logic Design 1 FLIP-FLOP. Digital Logic Design 1
2007 Introduction BK TP.HCM FLIP-FLOP So far we have seen Combinational Logic The output(s) depends only on the current values of the input variables Here we will look at Sequential Logic circuits The
More informationModule -5 Sequential Logic Design
Module -5 Sequential Logic Design 5.1. Motivation: In digital circuit theory, sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals but on
More informationDIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) COUNTERS
COURSE / CODE DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) COUNTERS One common requirement in digital circuits is counting, both forward and backward. Digital clocks and
More informationSequential Logic Basics
Sequential Logic Basics Unlike Combinational Logic circuits that change state depending upon the actual signals being applied to their inputs at that time, Sequential Logic circuits have some form of inherent
More informationWINTER 15 EXAMINATION Model Answer
Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate
More informationCHAPTER 6 COUNTERS & REGISTERS
CHAPTER 6 COUNTERS & REGISTERS 6.1 Asynchronous Counter 6.2 Synchronous Counter 6.3 State Machine 6.4 Basic Shift Register 6.5 Serial In/Serial Out Shift Register 6.6 Serial In/Parallel Out Shift Register
More informationIT T35 Digital system desigm y - ii /s - iii
UNIT - III Sequential Logic I Sequential circuits: latches flip flops analysis of clocked sequential circuits state reduction and assignments Registers and Counters: Registers shift registers ripple counters
More informationChapter 5 Flip-Flops and Related Devices
Chapter 5 Flip-Flops and Related Devices Chapter 5 Objectives Selected areas covered in this chapter: Constructing/analyzing operation of latch flip-flops made from NAND or NOR gates. Differences of synchronous/asynchronous
More informationB. Sc. III Semester (Electronics) - ( ) Digital Electronics-II) BE-301 MODEL ANSWER (AS-2791)
B. Sc. III Semester (Electronics) - (2013-14) Digital Electronics-II) BE-301 MODEL ANSWER (AS-2791) Section-[A] i. (B) ii. (A) iii. (D) iv. (C) v. (C) vi. (C) vii. (D) viii. (B) Ans-(ix): In JK flip flop
More informationDIGITAL CIRCUIT COMBINATORIAL LOGIC
DIGITAL CIRCUIT COMBINATORIAL LOGIC Logic levels: one zero true false high low CMOS logic levels: 1 => 0.7 V DD 0.4 V DD = noise margin 0 =< 0.3 V DD Positive logic: high = 1 = true low = 0 = false Negative
More informationUNIT-3: SEQUENTIAL LOGIC CIRCUITS
UNIT-3: SEQUENTIAL LOGIC CIRCUITS STRUCTURE 3. Objectives 3. Introduction 3.2 Sequential Logic Circuits 3.2. NAND Latch 3.2.2 RS Flip-Flop 3.2.3 D Flip-Flop 3.2.4 JK Flip-Flop 3.2.5 Edge Triggered RS Flip-Flop
More informationFlip Flop. S-R Flip Flop. Sequential Circuits. Block diagram. Prepared by:- Anwar Bari
Sequential Circuits The combinational circuit does not use any memory. Hence the previous state of input does not have any effect on the present state of the circuit. But sequential circuit has memory
More informationDEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING SUBJECT CODE: CS1202 ELECTRONIC CIRCUITS AND DIGITAL SYSTEMS (FOR THIRD SEMESTER IT & CSE)
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING SUBJECT CODE: CS1202 ELECTRONIC CIRCUITS AND DIGITAL SYSTEMS (FOR THIRD SEMESTER IT & CSE) TWO MARK QUESTIONS &ANSWERS CS 1202: ELECTRONIC CIRCUITS
More informationChapter 4: One-Shots, Counters, and Clocks
Chapter 4: One-Shots, Counters, and Clocks I. The Monostable Multivibrator (One-Shot) The timing pulse is one of the most common elements of laboratory electronics. Pulses can control logical sequences
More informationFLIP-FLOPS AND RELATED DEVICES
C H A P T E R 5 FLIP-FLOPS AND RELATED DEVICES OUTLINE 5- NAND Gate Latch 5-2 NOR Gate Latch 5-3 Troubleshooting Case Study 5-4 Digital Pulses 5-5 Clock Signals and Clocked Flip-Flops 5-6 Clocked S-R Flip-Flop
More informationScanned by CamScanner
NAVEEN RAJA VELCHURI DSD & Digital IC Applications Example: 2-bit asynchronous up counter: The 2-bit Asynchronous counter requires two flip-flops. Both flip-flop inputs are connected to logic 1, and initially
More informationReport on 4-bit Counter design Report- 1, 2. Report on D- Flipflop. Course project for ECE533
Report on 4-bit Counter design Report- 1, 2. Report on D- Flipflop Course project for ECE533 I. Objective: REPORT-I The objective of this project is to design a 4-bit counter and implement it into a chip
More informationECE 2274 Pre-Lab for Experiment Timer Chip
ECE 2274 Pre-Lab for Experiment 6 555 Timer Chip Introduction to the 555 Timer The 555 IC is a popular chip for acting as multivibrators. Go to the web to obtain a data sheet to be turn-in with the pre-lab.
More informationEMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP
EMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP 1 Chapter Overview Latches Gated Latches Edge-triggered flip-flops Master-slave flip-flops Flip-flop operating characteristics Flip-flop applications
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified)
Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate
More information16 Stage Bi-Directional LED Sequencer
16 Stage Bi-Directional LED Sequencer The bi-directional sequencer uses a 4 bit binary up/down counter (CD4516) and two "1 of 8 line decoders" (74HC138 or 74HCT138) to generate the popular "Night Rider"
More informationExperiment 8 Introduction to Latches and Flip-Flops and registers
Experiment 8 Introduction to Latches and Flip-Flops and registers Introduction: The logic circuits that have been used until now were combinational logic circuits since the output of the device depends
More informationChapter 4. Logic Design
Chapter 4 Logic Design 4.1 Introduction. In previous Chapter we studied gates and combinational circuits, which made by gates (AND, OR, NOT etc.). That can be represented by circuit diagram, truth table
More informationName Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers
EEE 304 Experiment No. 07 Name Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers Important: Submit your Prelab at the beginning of the lab. Prelab 1: Construct a S-R Latch and
More informationIntroduction. Serial In - Serial Out Shift Registers (SISO)
Introduction Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a group of flip-flops connected in a chain so that the output from one flip-flop becomes
More informationDigital Fundamentals: A Systems Approach
Digital Fundamentals: A Systems Approach Latches, Flip-Flops, and Timers Chapter 6 Traffic Signal Control Traffic Signal Control: State Diagram Traffic Signal Control: Block Diagram Traffic Signal Control:
More informationCHAPTER 1 LATCHES & FLIP-FLOPS
CHAPTER 1 LATCHES & FLIP-FLOPS 1 Outcome After learning this chapter, student should be able to; Recognize the difference between latches and flipflops Analyze the operation of the flip flop Draw the output
More informationAnalogue Versus Digital [5 M]
Q.1 a. Analogue Versus Digital [5 M] There are two basic ways of representing the numerical values of the various physical quantities with which we constantly deal in our day-to-day lives. One of the ways,
More informationMODULE 3. Combinational & Sequential logic
MODULE 3 Combinational & Sequential logic Combinational Logic Introduction Logic circuit may be classified into two categories. Combinational logic circuits 2. Sequential logic circuits A combinational
More informationIntroduction to Microprocessor & Digital Logic
ME262 Introduction to Microprocessor & Digital Logic (Sequential Logic) Summer 2 Sequential Logic Definition The output(s) of a sequential circuit depends d on the current and past states of the inputs,
More informationELECTRICAL ENGINEERING DEPARTMENT California Polytechnic State University
EECTRICA ENGINEERING DEPARTMENT California Polytechnic State University EE 361 NAND ogic Gate, RS Flip-Flop & JK Flip-Flop Pre-lab 7 1. Draw the logic symbol and construct the truth table for a NAND gate.
More informationChapter 7 Counters and Registers
Chapter 7 Counters and Registers Chapter 7 Objectives Selected areas covered in this chapter: Operation & characteristics of synchronous and asynchronous counters. Analyzing and evaluating various types
More informationNH 67, Karur Trichy Highways, Puliyur C.F, Karur District UNIT-III SEQUENTIAL CIRCUITS
NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF ELETRONICS AND COMMUNICATION ENGINEERING COURSE NOTES SUBJECT: DIGITAL ELECTRONICS CLASS: II YEAR ECE SUBJECT CODE: EC2203
More informationEECS 3201: Digital Logic Design Lecture 9. Ihab Amer, PhD, SMIEEE, P.Eng.
EECS 3201: Digital Logic Design Lecture 9 Ihab Amer, PhD, SMIEEE, P.Eng. Progress so far 2 Digital Logic Classification Digital Logic Combinational o/p s depend on i/p s only E.g. Logic Gates Sequential
More informationVignana Bharathi Institute of Technology UNIT 4 DLD
DLD UNIT IV Synchronous Sequential Circuits, Latches, Flip-flops, analysis of clocked sequential circuits, Registers, Shift registers, Ripple counters, Synchronous counters, other counters. Asynchronous
More informationSwitching Theory And Logic Design UNIT-IV SEQUENTIAL LOGIC CIRCUITS
Switching Theory And Logic Design UNIT-IV SEQUENTIAL LOGIC CIRCUITS Sequential circuits Classification of sequential circuits: Sequential circuits may be classified as two types. 1. Synchronous sequential
More informationLogic Design Viva Question Bank Compiled By Channveer Patil
Logic Design Viva Question Bank Compiled By Channveer Patil Title of the Practical: Verify the truth table of logic gates AND, OR, NOT, NAND and NOR gates/ Design Basic Gates Using NAND/NOR gates. Q.1
More informationRangkaian Sekuensial. Flip-flop
Rangkaian Sekuensial Rangkaian Sekuensial Flip-flop Combinational versus Sequential Functions Logic functions are categorized as being either combinational (sometimes referred to as combinatorial) or sequential.
More informationNH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN
NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT 4 SYNCHRONOUS SEQUENTIAL LOGIC Sequential circuits
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) WINTER 2018 EXAMINATION MODEL ANSWER
Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in themodel answer scheme. 2) The model answer and the answer written by candidate may
More informationReview of Flip-Flop. Divya Aggarwal. Student, Department of Physics and Astro-Physics, University of Delhi, New Delhi. their state.
pp. 4-9 Krishi Sanskriti Publications http://www.krishisanskriti.org/jbaer.html Review of Flip-Flop Divya Aggarwal Student, Department of Physics and Astro-Physics, University of Delhi, New Delhi Abstract:
More informationMODU LE DAY. Class-A, B, AB and C amplifiers - basic concepts, power, efficiency Basic concepts of Feedback and Oscillation. Day 1
DAY MODU LE TOPIC QUESTIONS Day 1 Day 2 Day 3 Day 4 I Class-A, B, AB and C amplifiers - basic concepts, power, efficiency Basic concepts of Feedback and Oscillation Phase Shift Wein Bridge oscillators.
More informationSolution to Digital Logic )What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it,
Solution to Digital Logic -2067 Solution to digital logic 2067 1.)What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it, A Magnitude comparator is a combinational
More informationDEPARTMENT OF COMPUTER SCIENCE & ENGINEERING
DRONACHARYA GROUP OF INSTITUTIONS, GREATER NOIDA Affiliated to Mahamaya Technical University, Noida Approved by AICTE DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING Lab Manual for Computer Organization Lab
More informationMUHAMMAD NAEEM LATIF MCS 3 RD SEMESTER KHANEWAL
1. A stage in a shift register consists of (a) a latch (b) a flip-flop (c) a byte of storage (d) from bits of storage 2. To serially shift a byte of data into a shift register, there must be (a) one click
More informationYEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING. EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall
YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall Objective: - Dealing with the operation of simple sequential devices. Learning invalid condition in
More informationUNIVERSITI TEKNOLOGI MALAYSIA
SULIT Faculty of Computing UNIVERSITI TEKNOLOGI MALAYSIA FINAL EXAMINATION SEMESTER I, 2016 / 2017 SUBJECT CODE : SUBJECT NAME : SECTION : TIME : DATE/DAY : VENUES : INSTRUCTIONS : Answer all questions
More informationTopic 8. Sequential Circuits 1
Topic 8 Sequential Circuits 1 Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Rabaey Chapter 7 URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk 1 Based on
More informationECB DIGITAL ELECTRONICS PROJECT BASED LEARNING PROJECT REPORT ON 7 SEGMENT DIGITAL STOP WATCH USING DECODER
ECB2212 - DIGITAL ELECTRONICS PROJECT BASED LEARNING PROJECT REPORT ON 7 SEGMENT DIGITAL STOP WATCH USING DECODER SUBMITTED BY ASHRAF HUSSAIN (160051601105) S SAMIULLAH (160051601059) CONTENTS >AIM >INTRODUCTION
More informationCombinational vs Sequential
Combinational vs Sequential inputs X Combinational Circuits outputs Z A combinational circuit: At any time, outputs depends only on inputs Changing inputs changes outputs No regard for previous inputs
More informationVivekananda College of Engineering and Technology Puttur (D.K)
Vivekananda College of Engineering and Technology Puttur (D.K) Analog and Digital Electronics Laboratory Manual 5CSL 37 Author Prof. Mahesh Prasanna K Assoc. Professor & Head, CSE kmpshastry@gmail.com
More informationCHAPTER 4: Logic Circuits
CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits
More informationECE 341. Lecture # 2
ECE 341 Lecture # 2 Instructor: Zeshan Chishti zeshan@pdx.edu October 1, 2014 Portland State University Announcements Course website reminder: http://www.ece.pdx.edu/~zeshan/ece341.htm Homework 1: Will
More informationThe NOR latch is similar to the NAND latch
5-2 NOR Gate Latch The NOR latch is similar to the NAND latch except that the Q and Q outputs are reversed. The set and clear inputs are active high, that is, the output will change when the input is pulsed
More informationEKT 121/4 ELEKTRONIK DIGIT 1
EKT 121/4 ELEKTRONIK DIGIT 1 Kolej Universiti Kejuruteraan Utara Malaysia Bistable Storage Devices and Related Devices Introduction Latches and flip-flops are the basic single-bit memory elements used
More informationLogic Design. Flip Flops, Registers and Counters
Logic Design Flip Flops, Registers and Counters Introduction Combinational circuits: value of each output depends only on the values of inputs Sequential Circuits: values of outputs depend on inputs and
More informationCounters
Counters A counter is the most versatile and useful subsystems in the digital system. A counter driven by a clock can be used to count the number of clock cycles. Since clock pulses occur at known intervals,
More informationDev Bhoomi Institute Of Technology Department of Electronics and Communication Engineering PRACTICAL INSTRUCTION SHEET
Dev Bhoomi Institute Of Technology Department of Electronics and Communication Engineering PRACTICAL INSTRUCTION SHEET LABORATORY MANUAL EXPERIMENT NO. 1 ISSUE NO. : ISSUE DATE: REV. NO. : REV. DATE :
More informationChapter 5 Synchronous Sequential Logic
Chapter 5 Synchronous Sequential Logic Sequential Circuits Latches and Flip-Flops Analysis of Clocked Sequential Circuits HDL Optimization Design Procedure Sequential Circuits Various definitions Combinational
More informationDigital Logic Design ENEE x. Lecture 19
Digital Logic Design ENEE 244-010x Lecture 19 Announcements Homework 8 due on Monday, 11/23. Agenda Last time: Timing Considerations (6.3) Master-Slave Flip-Flops (6.4) This time: Edge-Triggered Flip-Flops
More informationPHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops
PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops Objective Construct a two-bit binary decoder. Study multiplexers (MUX) and demultiplexers (DEMUX). Construct an RS flip-flop from discrete gates.
More informationDigital Circuits I and II Nov. 17, 1999
Physics 623 Digital Circuits I and II Nov. 17, 1999 Digital Circuits I 1 Purpose To introduce the basic principles of digital circuitry. To understand the small signal response of various gates and circuits
More informationSequential Circuits. Output depends only and immediately on the inputs Have no memory (dependence on past values of the inputs)
Sequential Circuits Combinational circuits Output depends only and immediately on the inputs Have no memory (dependence on past values of the inputs) Sequential circuits Combination circuits with memory
More informationDIGITAL REGISTERS. Serial Input Serial Output. Block Diagram. Operation
DIGITAL REGISTERS http://www.tutorialspoint.com/computer_logical_organization/digital_registers.htm Copyright tutorialspoint.com Flip-flop is a 1 bit memory cell which can be used for storing the digital
More informationAC103/AT103 ANALOG & DIGITAL ELECTRONICS JUN 2015
Q.2 a. Draw and explain the V-I characteristics (forward and reverse biasing) of a pn junction. (8) Please refer Page No 14-17 I.J.Nagrath Electronic Devices and Circuits 5th Edition. b. Draw and explain
More informationLATCHES & FLIP-FLOP. Chapter 7
LATCHES & FLIP-FLOP Chapter 7 INTRODUCTION Latch and flip flops are categorized as bistable devices which have two stable states,called SET and RESET. They can retain either of this states indefinitely
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 6 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter
More informationUNIT III. Combinational Circuit- Block Diagram. Sequential Circuit- Block Diagram
UNIT III INTRODUCTION In combinational logic circuits, the outputs at any instant of time depend only on the input signals present at that time. For a change in input, the output occurs immediately. Combinational
More informationVTU NOTES QUESTION PAPERS NEWS RESULTS FORUMS Registers
Registers Registers are a very important digital building block. A data register is used to store binary information appearing at the output of an encoding matrix.shift registers are a type of sequential
More informationLogic Devices for Interfacing, The 8085 MPU Lecture 4
Logic Devices for Interfacing, The 8085 MPU Lecture 4 1 Logic Devices for Interfacing Tri-State devices Buffer Bidirectional Buffer Decoder Encoder D Flip Flop :Latch and Clocked 2 Tri-state Logic Outputs
More informationSequential logic. Circuits with feedback. How to control feedback? Sequential circuits. Timing methodologies. Basic registers
equential logic equential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies cascading flip-flops for proper operation clock skew Basic registers shift registers
More informationCounter dan Register
Counter dan Register Introduction Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory.
More informationTEST-3 (DIGITAL ELECTRONICS)-(EECTRONIC)
1 TEST-3 (DIGITAL ELECTRONICS)-(EECTRONIC) Q.1 The flip-flip circuit is. a) Unstable b) multistable c) Monostable d) bitable Q.2 A digital counter consists of a group of a) Flip-flop b) half adders c)
More informationCHAPTER1: Digital Logic Circuits
CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits 1 Sequential Circuits Introduction Composed of a combinational circuit to which the memory elements are connected to form a feedback
More informationMODULAR DIGITAL ELECTRONICS TRAINING SYSTEM
MODULAR DIGITAL ELECTRONICS TRAINING SYSTEM MDETS UCTECH's Modular Digital Electronics Training System is a modular course covering the fundamentals, concepts, theory and applications of digital electronics.
More informationCCE RR REVISED & UN-REVISED KARNATAKA SECONDARY EDUCATION EXAMINATION BOARD, MALLESWARAM, BANGALORE G È.G È.G È..
CCE RR REVISED & UN-REVISED O %lo ÆË v ÃO y Æ fio» flms ÿ,» fl Ê«fiÀ M, ÊMV fl 560 003 KARNATAKA SECONDARY EDUCATION EXAMINATION BOARD, MALLESWARAM, BANGALORE 560 003 G È.G È.G È.. Æ fioê, d È 2018 S.
More informationMC9211 Computer Organization
MC9211 Computer Organization Unit 2 : Combinational and Sequential Circuits Lesson2 : Sequential Circuits (KSB) (MCA) (2009-12/ODD) (2009-10/1 A&B) Coverage Lesson2 Outlines the formal procedures for the
More informationPHY 351/651 LABORATORY 9 Digital Electronics The Basics
PHY 351/651 LABORATORY 9 Digital Electronics The Basics Reading Assignment Horowitz, Hill Chap. 8 Data sheets 74HC10N, 74HC86N, 74HC04N, 74HC03N, 74HC32N, 74HC08N, CD4007UBE, 74HC76N, LM555 Overview Over
More informationCHW 261: Logic Design
CHW 26: Logic Design Instructors: Prof. Hala Zayed Dr. Ahmed Shalaby http://www.bu.edu.eg/staff/halazayed4 http://bu.edu.eg/staff/ahmedshalaby4# Slide Digital Fundamentals CHAPTER 7 Latches, Flip-Flops
More informationDIGITAL ELECTRONICS: LOGIC AND CLOCKS
DIGITL ELECTRONICS: LOGIC ND CLOCKS L 6 INTRO: INTRODUCTION TO DISCRETE DIGITL LOGIC, MEMORY, ND CLOCKS GOLS In this experiment, we will learn about the most basic elements of digital electronics, from
More informationFlip-Flops and Related Devices. Wen-Hung Liao, Ph.D. 4/11/2001
Flip-Flops and Related Devices Wen-Hung Liao, Ph.D. 4/11/2001 Objectives Recognize the various IEEE/ANSI flip-flop symbols. Use state transition diagrams to describe counter operation. Use flip-flops in
More informationRS flip-flop using NOR gate
RS flip-flop using NOR gate Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two
More informationEEC 118 Lecture #9: Sequential Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #9: Sequential Logic Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Outline Review: Static CMOS Logic Finish Static CMOS transient analysis Sequential
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous)
Subject Code: 17320 Model Answer Page 1 of 32 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the Model answer scheme. 2) The model
More information3 Flip-Flops. The latch is a logic block that has 2 stable states (0) or (1). The RS latch can be forced to hold a 1 when the Set line is asserted.
3 Flip-Flops Flip-flops and latches are digital memory circuits that can remain in the state in which they were set even after the input signals have been removed. This means that the circuits have a memory
More informationExperiment # 9. Clock generator circuits & Counters. Digital Design LAB
Digital Design LAB Islamic University Gaza Engineering Faculty Department of Computer Engineering Fall 2012 ECOM 2112: Digital Design LAB Eng: Ahmed M. Ayash Experiment # 9 Clock generator circuits & Counters
More informationFlip-Flops. Because of this the state of the latch may keep changing in circuits with feedback as long as the clock pulse remains active.
Flip-Flops Objectives The objectives of this lesson are to study: 1. Latches versus Flip-Flops 2. Master-Slave Flip-Flops 3. Timing Analysis of Master-Slave Flip-Flops 4. Different Types of Master-Slave
More informationSwitching Circuits & Logic Design, Fall Final Examination (1/13/2012, 3:30pm~5:20pm)
Switching Circuits & Logic Design, Fall 2011 Final Examination (1/13/2012, 3:30pm~5:20pm) Problem 1: (15 points) Consider a new FF with three inputs, S, R, and T. No more than one of these inputs can be
More informationPart 4: Introduction to Sequential Logic. Basic Sequential structure. Positive-edge-triggered D flip-flop. Flip-flops classified by inputs
Part 4: Introduction to Sequential Logic Basic Sequential structure There are two kinds of components in a sequential circuit: () combinational blocks (2) storage elements Combinational blocks provide
More informationIntroduction to Sequential Circuits
Introduction to Sequential Circuits COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Introduction to Sequential Circuits Synchronous
More informationAsynchronous (Ripple) Counters
Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory. The chapter about flip-flops introduced
More informationModeling Digital Systems with Verilog
Modeling Digital Systems with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 6-1 Composition of Digital Systems Most digital systems can be partitioned into two types
More informationEEE2135 Digital Logic Design Chapter 6. Latches/Flip-Flops and Registers/Counters 서강대학교 전자공학과
EEE235 Digital Logic Design Chapter 6. Latches/Flip-Flops and Registers/Counters 서강대학교 전자공학과 . Delay and Latches ) Signal Storage a. as voltage level static memory b. as charges dynamic memory 2) Delays
More informationDepartmentofElectronicEngineering NEDUniversity ofengineering &Technology LABORATORY WORKBOOK DIGITAL LOGIC DESIGN (TC-201)
DepartmentofElectronicEngineering NEDUniversity ofengineering &Technology LABORATORY WORKBOOK DIGITAL LOGIC DESIGN (TC-201) Instructor Name: Student Name: Roll Number: Semester: Batch: Year: Department:
More informationA MISSILE INSTRUMENTATION ENCODER
A MISSILE INSTRUMENTATION ENCODER Item Type text; Proceedings Authors CONN, RAYMOND; BREEDLOVE, PHILLIP Publisher International Foundation for Telemetering Journal International Telemetering Conference
More informationOFC & VLSI SIMULATION LAB MANUAL
DEVBHOOMI INSTITUTE OF TECHNOLOGY FOR WOMEN, DEHRADUN - 24847 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING Prepared BY: Ajay Kumar Gautam Asst. Prof. Electronics & Communication Engineering
More informationPhysics 120 Lab 10 (2018): Flip-flops and Registers
Physics 120 Lab 10 (2018): Flip-flops and Registers 10.1 The basic flip-flop: NAND latch This circuit, the most fundamental of flip-flop or memory circuits, can be built with either NANDs or NORs. We will
More information