Switching Circuits & Logic Design

Transcription

1 Switching Circuits & Logic Design Jie-Hong oland Jiang 江介宏 Department of Electrical Engineering National Taiwan University Fall 22

2 Latches and Flip-Flops 2

3 Outline Introduction Set-reset latch Gated D latch Edge-triggered D flip-flop S- flip-flop J-K flip-flop T flip-flop Flip-flops with additional inputs Summary 3

4 Introduction Combinational circuits Output is a function depending on the present input, but not past inputs Given an arbitrary input, a combinational circuit produces only one possible output (after certain delay) Not necessarily acyclic (without feedback) Sequential circuits Output is a function depending on the past sequence of inputs Must be cyclic (with feedback) Synchronous sequential circuits With memory devices (registers, latches) Asynchronous sequential circuits Without memory devices 4

5 Introduction Combinational circuits (without memory) x x 2 x 3 f z = f(x,x 2,x 3 ) Sequential circuits (with memory) x s mem f g z = f(x,s) s + = g(x,s) time index z = f(x,s ) z = f(x,g(x,s )) z2 = f(x2,g(x,g(x,s))) 5

6 Introduction To construct a system (e.g., circuit, neural network, etc.) that remembers something about the past history of the inputs Need feedback! Closed loops formed in a circuit connection 6

7 Introduction Memory devices Memory devices Latches and flip-flops can assume one of two stable output states, and have one or more inputs that can cause the output state to change Latch Have no clock input Flip-flip Change output state in response to a clock input, but not a data input 7

8 Introduction Feedback Unstable Oscillator Feedback X X Inverter with feedback Oscillation at inverter output Stable Memory (-bit) 8

9 9 Set-eset Latch S- latch S P S P S P S P (a) Stable: = (b) Set: S: : (b) eset: : : (a) Stable: =

10 Set-eset Latch Cross-coupled form S- latch symbol ' ' L S S eset Set eset Set directly above S (different from the cross-coupled form)

11 Set-eset Latch Improper S- latch operation When S = =, the circuit is unstable Disallow S = = for S- latch S P

12 Set-eset Latch Timing diagram S ' є є t t 2 t 3 t 4 t S t +є t 3 +є : two NO-gate delay The duration of the S (or ) input pulse must normally be no less than in order for a change in the state of to occur 2

13 Set-eset Latch Operation Next-state equation (or characteristic equation): + = S+' (S=, i.e., S== disallowed) Present (or current) state The state of the output of the latch or flip-flop at the time the input signals are applied (or changed) Next state + The state of the output after the latch or flip-flop has reacted to these input signals S(t) (t) (t) (t+ ) - - hold reset set prohibited S(t) (t) (t) (t+є)=s(t)+'(t)(t) 3

14 Set-eset Latch Application Switch debouncing Note: only work for a double throw switch, switching between two contacts (but not for a single throw switch) why? +V b a S S Switch at a Bounce at a Switch between a and b Bounce at b Switch at b 4

15 Set-eset Latch Alternative Implementation S- latch S- latch using NAND gates S S + S S ' - - hold reset set prohibited L ' Inputs S and are active low 5

16 Gated D Latch Gated D latch G D S D G L ' Truth table Symbol D L G D + hold ( + = ) GD G ' transparent ( + = D) + = G'+GD 6

17 Edge-Triggered D Flip-Flop Unlike D latch, D flip-flip output changes only in response to the clock, not to a change in D rising (or positive) edge triggered (-to- transition on clock) falling (or negative) edge triggered (-to- transition on clock) ' Ck FF D ' Ck FF D D + + = D ising-edge trigger Falling-edge trigger Truth table 7

18 Edge-Triggered D Flip-Flop Timing diagram (falling-edge trigger) D Ck 8

19 Edge-Triggered D Flip-Flop Implementation D flip-flop (rising-edge trigger) Composed of two gated D latches CLK D D L G P D 2 2 L 2 G 2 Time analysis CLK=G 2 L 2 hold L hold L 2 hold If L starts following D before L 2 takes on P, the FF will not function properly G D P 9

20 Edge-Triggered D Flip-Flop Setup Time and Hold Time Propagation delay: t p The time between the active edge of the clock and the resulting change in the output Setup time: t su The amount of time D must be stable before the active edge Hold time: t h The amount of time D must hold the same value after the active edge t su t h D allowed to change D Ck t p t p 2

21 Edge-Triggered D Flip-Flop Determine Minimum Clock Period Simple flip-flop circuit example (t p 5ns, t su 3ns, inverter delay 2ns) CLK t su t p D D inv delay CLK Setup time not satisfied t su t su t p t p extra 5ns inv delay inv delay Setup time satisfied Minimum clock period 2

22 S- Flip-Flop Similar to S- latch but with clock input Same truth table and characteristic equation Interpretation of + is different Latch: + is the value of after the propagation delay through the latch FF: + is the value that assumes after the active clock edge S- flip-flop S Operation summary: Ck ' changes at clock edges S== S=,= S=,= S== no state change set to (after active Ck edge) reset to (after active Ck edge) not allowed 22

23 S- Flip-Flop Implementation S- flip-flop (master-slave flip-flop) Composed of two S- latches Only allow the S and inputs to change while CLK is high S S P S CLK Master 2 Slave P' ' 2 ' Time analysis CLK CLK S P t t 2 t 3 t 4 t 5 ising-edge-triggered FF: Inputs can change while CLK is low Master-slave FF: Incorrect if inputs change while CLK is low 23

24 J-K Flip-Flop J-K flip-flop is an extended version of S- flip-flop + = J'+K' J corresponds to S (Jump to ); K corresponds to (Klear to ) State toggled when J=K= Clk J-K flip-flop ' K FF CK J J K J K + t p t p t p Hold t t 2 t 3 Clear to Jump to Toggle CLK J K S Master P P' S 2 Slave ' 2 ' 24

25 T Flip-Flop T flip-flop ' Ck FF T T + hold toggle + = T'+T' = T T = + = T = + = ' Ck T t p t p t t 2 t 3 t 4 25

26 T Flip-Flop Implementation Conversion of J-K to T Connect J and K inputs of a J-K FF together + =J'+K' + =T'+T' Conversion of D to T Let D = T + =D + = T ' ' K CK J Ck D Clk T Clk T 26

27 Flip-Flops with Additional Inputs Asynchronous Clear and Preset Flip-flops often have additional inputs to set the flip-flops to an initial state independent of the clock Ck D PreN ClrN + ClrN ' Ck D PreN x x x,, x x x x (not allowed) (no change) ClrN and PreN are asynchronous clear and preset inputs (they override the Ck and D inputs) ClrN and PreN are active low signals When ClrN=PreN=, the FF is in normal operation should not be applied to ClrN and PreN simultaneously 27

28 Flip-Flops with Additional Inputs Asynchronous Clear and Preset Timing diagram for D flip-flop with asynchronous clear and preset CLK D ClrN PreN t t 2 t t

29 Flip-Flops with Additional Inputs Clock Enable D flip-flop with clock enable (CE) D-CE symbol D CE Ck ' Implementation : gating the clock Clk En D Ck ' Implementation 2: no clock gating Loss of synchronization when ) clock arrive at some FFs at different times 2) En changes at the wrong time CE + = D = (CE)' + D in (CE) D in D No synchronization problem Clk Ck ' 29

30 Summary Latch (w/o clock input) vs. flip-flop (w/ clock input) Propagation delay, setup time, hold time Present (current) state, next state Characteristic (next-state) equations + = S+' (S=) (S- latch or flip-flop) + = GD+G' (gated D latch) + = D (D flip-flop) + = D CE+ CE' (D-CE flip-flop) + = J'+K' (J-K flip-flop) + = T = T'+T' (T flip-flop) estrictions For S- latch/flip-flop, S and can not be simultaneously For master-slave S- flip-flop, S and should not change during the half clock cycle preceding the active edge Setup and hold time constraints 3