CSE140: Components and Design Techniques for Digital Systems. More D-Flip-Flops. Tajana Simunic Rosing. Sources: TSR, Katz, Boriello & Vahid

Transcription

1 CSE140: Components and esign Techniques for igital Systems More -Flip-Flops Tajana Simunic Rosing

2 Where we are now. What we covered last time: SRAM cell, SR latch, latch, -FF What we ll do next: -FF review, registers, pattern recognizers Upcoming deadlines: ZyBook today: HW#4 assigned, due next Tuesday uiz #4 on today! Midterm #2 Coming up in 14 days generally harder than Midterm#1 Cumulative

3 Bit Storage Overview SR latch S (set) R (reset) Level-sensitive SR latch S S1 C R R1 C S R latch Clk latch mm Cm master flip-flop latch s s Cs s servant S=1 sets to 1, R=1 resets to 0. Problem: SR=11 yield undefined. S and R only have effect when C=1. We can design outside circuit so SR=11 never happens when C=1. Problem: avoiding SR=11 can be a burden. SR can t be 11 if is stable before and while C=1, and will be 11 for only a brief glitch even if changes while C=1. Problem: C=1 too long propagates new values through too many latches: too short may not enable a store. Only loads value present at rising clock edge, so values can t propagate to other flipflops during same clock cycle. Tradeoff: uses more gates internally than latch, and requires more external gates than SR but gate count is less of an issue today. 3

4 Comparison of latches and flip-flops positive edge-triggered flip-flop FF G level-sensitive latch latch Sources: TSR, Katz, Boriello & Vahid 4

5 Flip-Flops Assume that the data in all -FFs is initially 0. Input Y=1. When Clk goes from 0->1, the stored values in -FFs are: Y Two latches inside each flip-flop Clk Clk_A Clk_B A. 1=1, 2=0, 3=0, 4=0 for both clock A & B B. 1=1, 2=1, 3=1, 4=1 for clock A 1=1, 2=0, 3=0, 4=0 for clock B C. 1=1, 2=1, 3=1, 4=1 for both clocks. More information is needed to determine the answer E. None of the above Sources: TSR, Katz, Boriello & Vahid 5

6 Rising vs. Falling Edge Flip-Flop The triangle means clock input, edge triggered Symbol for rising-edge triggered flip-flop rising edges Clk Symbol for falling-edge triggered flip-flop Clk falling edges Internal design: Just invert servant clock rather than master 6

7 Enabled -FFs Inputs:,, EN The enable input (EN) controls when new data () is stored Function EN = 1: passes through to on the clock edge EN = 0: the flip-flop retains its previous state EN Internal Circuit Symbol 0 1 EN

8 Additional -FF Features Reset (set state to 0) R synchronous: new = R' old (when next clock edge arrives) asynchronous: doesn't wait for clock Preset or set (set state to 1) S (or sometimes P) synchronous: new = old + S (when next clock edge arrives) asynchronous: doesn't wait for clock Both reset and preset new = R' old + S (set-dominant) new = R' old + R'S (reset-dominant) Selective input capability (input enable or load) L or EN multiplexor at input: new = L' + L old load may or may not override reset/set (usually R/S have priority) Complementary outputs and ' 8

9 Registers and Counters 9 Sources: TSR, Katz, Boriello & Vahid

10 Building blocks with FFs: Basic Register OUT1 OUT2 OUT3 OUT4 IN1 IN2 IN3 IN4 I3 I2 I1 I0 reg(4)

11 Shift register Holds & shifts samples of input OUT1 OUT2 OUT3 OUT4 IN 11

12 Pattern Recognizer Combinational function of input samples OUT OUT1 OUT2 OUT3 OUT4 IN 12

13 esign of a Universal Shift Register left_in left_out clear s0 s1 output input right_out right_in clock clear s0 s1 new value output output value of FF to left (shift right) output value of FF to right (shift left) input Nth cell to N-1th cell to N+1th cell CLEAR s0 and s1 control mux [N-1] (left) Input[N] [N+1] (right)

14 Counters Sequences through a fixed set of patterns OUT1 OUT2 OUT3 OUT4 IN 14

15 General Counters efault operation: count up A- counter output A- parallel load data LOA enables data load RCO ripple carry out CLR clears data EN counter enable "1" "0" "1" "1" "0" "0" EN RCO C C B B A A LOA CLR "1" "0" "0" "0" "0" EN RCO C C B B A A LOA CLR 15

16 Finite State Machines 16 Sources: TSR, Katz, Boriello & Vahid

17 Circuit Specifications Combinational Logic Truth tables, Boolean equations, logic diagrams (no feedback) Sequential Networks: State iagram (Memory) State and Excitation Tables Characteristic Expression Logic iagram (FFs and feedback loops) Y A B C Combinational X RTL: Register-Transfer Level escription 17

18 Finite State Machines: Two Bit Counter Example Symbol/ Circuit Current state Next State 2 bit Counter S 0 S 1 S 1 S 2 S 2 S 3 S 3 S 0 S 0 1 (t) 0 (t) 1 (t+1) 0 (t+1) S 3 S 1 S 2 State iagram State Table Sources: TSR, Katz, Boriello & Vahid

19 Circuit with 2 flip flops Circuit with one flip flop Sources: TSR, Katz, Boriello & Vahid Which is the most likely circuit realization of the two bit counter? State Table 1 (t) 0 (t) 1 (t+1) 0 (t+1) A. Combinational circuit Circuit with no flip flops B. C. 0 (t) Combinational circuit 1 (t) 0 (t) 1 (t) Combinational circuit

20 Two Bit Counter Circuit State Table 1 (t) 0 (t) 1 (t+1) 0 (t+1) (t) 1 (t) We store the current state using -flip flops so that: Inputs to the combinational circuit don t change while the next output is computed The transition to the next state only occurs at the rising edge of the clock 0 (t) = 0 (t) 1 (t) = 0 (t) 1 (t) + 0 (t) 1 (t) Implementation of 2-bit counter Sources: TSR, Katz, Boriello & Vahid