CSE Latches and Flip-flops Dr. Izadi. NOR gate property: A B Z Cross coupled NOR gates: S M S R Q M
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1 CSE-4523 Latches and Flip-flops Dr. Izadi NOR gate property: A B Z A B Z Cross coupled NOR gates: S M S R M R S M R S R S R M S S M R R
2 S ' Gate R Gate S R S G R S R (t+) S G R
3 Flip_flops:. S-R flip-flop S R (t+) S CLK R 2. D flip-flop D S D S R (t+) R D D (t+) 3. J K flip-flop J K (t+) J K 4. T flip-flop T J T J K (t+) K T T (t+)
4 4-3 Figure 4-3 Synchronous Clocked Sequential Circuit Inputs Combinational circuit Clock pulses Flip-flops Outputs (a) Block diagram (b) Timing diagram of clock pulses 2 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS
5 4-6 Table 4- Flip-Flop Characteristic Table (a) JK Flip-Flop (b) SR Flip-Flop J K (t ) Operation S R (t ) Operation (t) No change (t) No change Reset Reset Set Set t () Complement? Undefined (c) D Flip-Flop (d) T Flip-Flop D (t ) Operation T (t ) Operation Reset (t) No change Set t () Complement 2 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS
6 4-7 Figure 4-6 JK Flip-Flop with Direct Set and Reset S J C K R S R C J K Undefined No change Complement (a) Graphic symbols (b) Function table 2 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS
7 CSE-4523 Analysis of Sequential Circuits Dr. Izadi Analysis Procedure:. Obtain flip-flop input equations 2. Write down characteristic table of each type of flip-flop in use 3. Develop state table 4. Obtain state diagram Example #: J A A K A A CLK J B B K B B Step : Flip-flop input equations and output equation J A = K A = B = B J B = A ' K B = A Step 2: Characteristic Table J K (t+) (t) '(t)
8 CSE-4523 Analysis of Sequential Circuits Dr. Izadi Step 3: State Table PS A B J A K A J B K B NS A B Step 4: State Diagram 2
9 CSE-4523 Analysis of Sequential Circuits Dr. Izadi Example #2: A S A A B R A A A ' B CLK Z ' B B ' S B R B B B Step : Flip-flop input equations and output equation S A = ( A + ') = A R A = A B + B S B = B R B = B ' Z = A ' B ' Step 2: Characteristic Table S R (t+) (t) - 3
10 CSE-4523 Analysis of Sequential Circuits Dr. Izadi Step 3: State Table PS A B S A R A S B R B NS A B Z Step 4: State Diagram / / / / / / / / 4
11 4-22 Figure 4-9 Logic Diagram and State Table for D A = A Y D A Z Y C (a) Clock Present state A Inputs Y Next state A (b) State table Output Z 2 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS
12 CSE-4523 Analysis of Sequential Circuits Dr. Izadi Example #3: B C D A D A A ' D A ' B C D B ' C B D B B B ' D ' A ' C D C ' D D C C C ' D D D D CLK D Step : Flip-flop input equations D A = B C D + A D ' D B = B ' C D + B C '+ B D ' D C = A ' C ' D + C D' D D = D ' 5
13 CSE-4523 Analysis of Sequential Circuits Dr. Izadi Step 2: Characteristic Table D (t+) Step 3: State Table PS A B C D D A D B D C D D NS A B C D 6
14 CSE-4523 Analysis of Sequential Circuits Dr. Izadi Step 4: State Diagram 7
15 4-36 (a) JK Flip-Flop (b) SR Flip-Flop (t) (t ) J K (t) (t ) S R (c) D Flip-Flop (d) T Flip-Flop (t) (t ) D (t) (t ) T Table 4- Flip-Flop Excitation Table M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS 2 Prentice Hall, Inc.
16 CSE-4523 Design of Sequential Circuits Dr. Izadi DESIGN PROCEDURE. Word description. 2. State diagram. 3. Assign binary values. 4. Decide on type of flip flops. 5. Excitation table for the flip flop. 6. State table. 7. Generate simplified logic equations for flip flop inputs and system outputs. 8. Draw logic diagram. Example #: Using D flip-flops, design a to 9 synchronous counter. State diagram
17 D Flip-Flop Excitation Table (t) (t+) D State Table PRESENT NET STATE STATE A B C D A B C D D A D B D C D D 2
18 Karnaugh Map A B C D m D A = B C D + A D ' C D A B m D B = B ' C D + B C '+ B D ' 3
19 C D A B m D C = A ' C ' D + C D' C D A B m D D = D ' 4
20 Circuit B C D A D A A ' D A ' B C D B D A B ' C B B ' D ' A ' C D C D C C ' D C ' D D D D CLK D 5
21 Example #2:. State diagram / / / / / / / / 2. Use JK flip flops 3. Flip flop Excitation Table PRESENT STATE NET STATE J K (t) (t+) 6
22 4. State Table PRESENT STATE INPUT NET STATE FLIP-FLOP INPUTS OUTPUT A B A B J A K A J B K B Z 5. Karnaugh Map B A m m m 3 m 2 m 4 m 5 m 7 m 6 J A = B ' B A m m m 3 m 2 m 4 m 5 m 7 m 6 K A = B 7
23 B A m m m 3 m 2 m 4 m 5 m 7 m 6 J B = B A m m m 3 m 2 m 4 m 5 m 7 m 6 K B = A ' + ' A = A + B A m m m 3 m 2 m 4 m 5 m 7 m 6 Z = A ' B 6. Schematic A J A A B K A A Z CLK J B B A K B B 8
24 Example #3: Using JK flip-flops, design an up/down synchronous counter as specified below. The counter counts up if input is and it counts down when is. State Diagram x= x= x= x= x= x= x= x= x= x= x= x= x= x= x= x= Use JK flip flops 9
25 Flip flop Excitation Table State Table PRESENT STATE NET STATE (t) (t+) J K PRESENT STATE INPUT NET STATE A B C A B C J A K A J B K B J C K C
26 Karnaugh Map C A B m m m 3 m 2 m 4 m 5 m 7 m 6 m 2 m 3 m 5 m 4 m 8 m 9 m m J A = ' B ' C ' + B C C A B m m m 3 m 2 m 4 m 5 m 7 m 6 m 2 m 3 m 5 m 4 m 8 m 9 m m K A = ' B ' C ' + B C
27 C A B m m m 3 m 2 m 4 m 5 m 7 m 6 m 2 m 3 m 5 m 4 m 8 m 9 m m J B = ' C ' + C = C. C A B m m m 3 m 2 m 4 m 5 m 7 m 6 m 2 m 3 m 5 m 4 m 8 m 9 m m K B = ' C ' + C = C. J C = K C = 2
28 Schematic B C J A A ' B K A A ' C CLK C J B B K B B + 5 V J C C + 5 V K C C 3
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