EE 200 Problem Set 3 Cover Sheet Fall 2015

Transcription

1 EE 200 Problem Set 3 Cover Sheet Fall 2015 Last Name (Print): First Name (Print): PSU User ID (e.g. xyz1234): Section: Submission deadline: All work is due by Monday 21 September at 4 pm. Written work must be turned into the homework slot outside 121 EE East. Your Multisim file must be uploaded to the Problem Set 3 drop box. Problem Weight Score The solution submitted for grading represents my own analysis of the problem and not that of another student. Signature: Neatly print the names of any students you collaborated with on this assignment.

2 Problem 9: (30 points) This semester you will realize a Moore finite state machine for controlling the behavior of a car s tail lamps using four different design tools: Discrete logic using NAND gates and D-type flip-flops A complex programmable logic device using hardware descriptive language An embedded microcontroller programmed using the C programming language The mydaq using the LabVIEW programming environment This problem requires you to design a discrete-logic circuit that realizes the Moore finite state machine for controlling the tail lamps. To receive credit you must base your design on information provided below. Please note that this design is different than the one considered in Problem 8. The tail lamp system has two outputs, the left tail lamp, LL and the right tail lamp, RL; they are both true when lit. The tail lamp system has four inputs The finite state machine has the four input signals defined in Table 1. The input signals Ls, Rs and H are observed synchronously with respect to a 5 Hz clock signal, while B is an asynchronous input. Signal Symbol Description Left Turn Switch Ls True when activated Right Turn Switch Rs True when activated Hazard Flasher Switch H True when activated Brake Switch B True when activated Table 1: The input signals. Because the Left Turn Switch and Right Turn Switch cannot be activated simultaneously, you will need to implement logic to ensure that simultaneous activation is treated as false for both inputs. The finite state machine has four states defined in Table 2. State QA QB Description S0 0 0 Both tail lights are on S1 0 1 Left tail light is on S2 1 0 Right tail light is on S3 1 1 Both tail lights are off Table 2: The state assignments. The system has the following desired behavior: When no switches are activated, the tail lights are off When the left turn switch is activated, the left tail light will illuminate. If the switch remains activated, the left tail lamp will turn off on the next clock cycle. The light will continue to flash on and off on subsequent clock cycles.

3 When the right turn switch is activated, the right tail light will illuminate. If the switch remains activated, the right tail lamp will turn off on the next clock cycle. The light will continue to flash on and off on subsequent clock cycles. When the hazard flasher switch is activated, both tail lights will illuminate. If the switch remains activated, the tail lamps will turn off on the next clock cycle. The lights will continue to flash on and off on subsequent clock cycles. The hazard flasher is more important than the turn signals, so they are activated regardless of the L and R inputs. When is true, all the tail lights should illuminate until B is false. As the input B is more important than turn signals and hazard flashers, this behavior must hold regardless of the other inputs and current state. The state table for the system is given in Table 3. Present State Inputs Next State Outputs QA QB H L R DA DB LL RL S S S S S S S S S S S S S S S S S S S S S S S S S S S S Table 3: State table of the finite state machine. This problem requires you to design a discrete-logic circuit that realizes the Moore finite state machine for controlling the tail lights. To receive credit, you must base your design on the state table provided. In addition, you must use the notation for the states, inputs and outputs defined in this problem.

4 1. (5 points) Neatly draw the state transition diagram for the system based on the state table and the description of operations provided. 2. (14 points) Using the state table provided and the five-variable Karnaugh map in Figure 1 (A), determine the input equations for the two D-type flip-flops DA and DB. To receive credit, your solution must use the variable assignments appearing in Figure 1 (A). No credit will be given if you alter the location of the variables in the Karnaugh map provided. 3. (2 points) Using the state table provided and the two-variable Karnaugh map in Figure 1 (B), determine the output equations for LS and RS. To receive credit, your solution must use the variable assignments appearing in Figure 1 (B). No credit will be given if you alter the location of the variables in the Karnaugh map provided. 4. (9 points) Realize the finite state machine using at most eight two-input NAND gates, six three-input NAND gates, four four-input NAND gates, one eight-input NAND gate and two D-type flip-flops. Assume that each D-type flip-flop has an asynchronous input labeled CLR that drives the flip-flop output to logic low whenever the value of CLR is logic high. If it is necessary to invert a logic level, use one of the NAND gates. Neatly sketch the logic diagram that clearly shows the inputs CLK, H, L, R, B and the output signals LS and RS. You should include the logic needed to prevent L and R from asserting simultaneously. Figure 1: (A) Five-variable Karnaugh map and (B) two-variable Karnaugh maps.

5 Problem 10: (25 points) The network in Figure 2 implements a passive filter with the input voltage f(t) and the output voltage y(t). Figure 2: Passive filter network. 1. (8 points) Show that the frequency response of the network in Figure 2 is 1 H(jω) = K jω ωc + 1 Express the parameters K and ω c in terms of R1, R2, and L. 2. (5 points) The DC gain of the network is the value of the frequency response function when the input frequency, ω, is set to zero, while the high frequency gain is the magnitude of the frequency response function as the input frequency approaches infinity. a. (2 points) Determine the DC gain of the filter network in Figure 2. b. (2 points) Determine the high frequency gain of the filter network in Figure 2. c. (1 point) Does this network realize a low-pass or high-pass filter? Justify your answer in one or two sentences. Ω 3. (12 points) Suppose that the values of the network components are R1 = 12 Ω, R2 = 28 Ω, and L = 40 mh. Using the discussion on Bode plots and the Exercise 1 solution in Laboratory 4, sketch the Bode magnitude and phase plots of the network in Figure 2. To receive credit: Plot the straight-line approximation of the true magnitude response in db as a function of frequency, ω, from 10 rad sec to 100,000 rad sec using the semilog graph paper included with the problem set. Plot the straight-line approximation of the true phase of the frequency response function in degrees as a function of frequency, ω, from 10 rad sec to 100,000 rad sec using the semilog graph paper included with the problem set. Label the axes with appropriate units and provide numeric values. Indicate the slope of each straight-line segment as well as the corner frequency, ω c.

6 Problem 11: (20 points) Verify your result in Problem 10 using Multisim. 1. (4 points) Using the values R1 = 12 Ω, R2 = 28 Ω, and L = 40 mh and the node labels 1 and 2 indicated in Figure 2, complete the SPICE model in Figure 3 for the passive filter. 2. (20 points) Create a custom Multisim component called RL_filter using the SPICE subcircuit representation from your completed Figure 3. Following Laboratory 4 Exercise 3, determine the true magnitude and phase response of the network in Figure 2. a. (2 points) Using the results from Multisim, specify the corner frequency ω c in units of Hertz and rad sec. b. (2 points) Using the results from Multisim, specify the magnitude of the gain in units of V/V and db at DC and two decades above the corner frequency. c. (2 points) Using the results from Multisim, specify the phase of the frequency response function in units of degrees at DC and two decades above the corner frequency. d. (10 points) Upload your Multisim file to the problem set 3 dropbox. To receive credit for your work, name your file as follows lastname_firstname_ps3_p11.ms12. The Multisim file must contain the custom RL filter and show the filter appropriately connected to an AC source and the Bode-Plotter-XBP1. Problem 12: (25 points) 1. (8 points) Review the LabVIEW coding standards presented in Lecture 3, then open and review the subvi ps3p12part1.vi included with Problem Set 3. This subvi realizes the following combinational logic equation D A = x + y + Q A + Q B where x, y, QA and QB are Boolean inputs and DA is a Boolean output. 2. (17 points) For each of the following LabVIEW block diagrams, determine the numeric value of the indicator after the VI completes execution. Reason an answer based on your understanding of the LabVIEW programming environment. In order to verify your answer and improve your understanding of the code, it is recommended that you use LabVIEW to execute the code with the Highlight Execution option enabled. a. (6 points) Figure 4: Block diagram for Problem 12, part 2a.

7 b. (6 points) c. (5 points) Figure 5: Block diagram for Problem 12, part 2b. Figure 6: Block diagram for Problem 12, part 2c. Note the block diagram is shown for both values of the case structure.

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