Implementation and Analysis of Area Efficient Architectures for CSLA by using CLA

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1 Volume-6, Issue-3, May-June 2016 International Journal of Engineering and Management Research Page Number: Implementation and Analysis of Area Efficient Architectures for CSLA by using CLA Anshu Kumari 1, Kamal Niwaria 2 ABSTRACT In the design of Integrated circuit area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data processing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this paper 16 bit, 32 bit, 64 bit and 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. Here we are proposed the carry look-ahead (CLA) adder replacing the ripple carry adder (RCA). However, the Regular CSLA is still area-consuming due to the dual Ripple- Carry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single CLA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA; the Modified SQRT CSLA has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT CSLA provide better outcomes than the Regular Linear CSLA and Regular SQRT CSLA respectively. This project was aimed for implementing high performance optimized FPGA architecture. Modelsim 6.3g is used for simulating the CSLA and synthesized using Xilinx PlanAhead14.3. Then the implementation is done in Spartan3E FPGA Kit. In this proposed architecture we are implement 16- bit carry select adder. A simple approach is proposed in this paper to reduce the area of linear CSLA architecture. The reduced number of gates of this work offers the great advantage in the reduction of area and also the total power. The modified CSLA architecture is therefore, low area, low power, simple and efficient for VLSI hardware implementation. It would be interesting to test the design of the modified 16-b linear CSLA. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Keywords--- CSLA, SQRT, VLSI I. INTRODUCTION Design of area- and power-efficient high-speed data path logic systems are one of the most substantial areas of research in VLSI system design. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the next position. The CSLA is used in many computational systems to alleviate the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum. However, the CSLA is not area efficient because it uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input cin = 0 and cin = 1, then the final sum and carry are selected by the multiplexers (mux). The basic idea of this work is to use Binary to Excess-1 Converter (BEC) instead of RCA with cin = 1 in the regular CSLA to achieve lower area and power consumption. The main advantage of this BEC logic comes from the lesser number of logic gates than the n-bit Full Adder (FA) structure. The details of the BEC logic are discussed. II. EXITING METHOD In the existing method we are using 16-bit carry select adder. Only Carry Select Adder is the fastest adders which are used in many data-processing processors to perform fast arithmetic operation. From the Design of the CSLA, it is clear that there is scope for reducing the area and delay in the CSLA. So we propose the new adder with less area and time delay compared to previous method. Design block: 753 Copyright Vandana Publications. All Rights Reserved.

2 of the replaced RCA with Cin=1.Fig shows the modified diagram 16-bit SQRT CSLA. The number of bits required for BEC logic is 1 bit more than the RCA bits. The modified block diagram is also divided into various groups of variable sizes of bits with each group having the ripple carry adders, BEC and mux. First group contain one RCA which is having input of lower significant bit and carry in bit and produces result of sum(1:0) and carry out which is acting as mux selection line for the next group. The XOR gate in BEC of Modified CSLA is replaced with the optimized XOR gate in AOI of Modified Area Efficient CSLA.With BEC there is reduction of gates by replacing n bit RCA with n+1 bit BEC. When the optimized XOR gate is used in Modified CSLA, it is verified that there is large reduction in number of gates. The MUX is used to select either the BEC output or the inputs given directly to a BEC circuit. In this design, the major function of MUX is to derive the adder speed. III. PROPOSED METHOD In this paper we implement 16-bit carry select adder. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. The Binary to Excess-1 converter (BEC) is used instead of RCA. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. Design block: IV. ARCHITECTURE OF MODIFIED 16- BIT REGULAR CSLA USING CLA This architecture is similar to regular 16-bit regular CSLA, the only change is that, we replace RCA with CLA among the two available RCAs in a group with a CLA and BEC. This BEC has a feature that it can perform the similar operation as that of the replaced RCA with Cin=1. Fig. 5 shows the Modified block diagram of 16-bit regular CSLA. The number of bits required for BEC logic is 1 bit more than the RCA bits. The modified block diagram is also divided into various groups of variable sizes of bits with each group having the carry look-ahead adders, BEC and corresponding mux. Group 0 contain one CLA only which is having input of lower significant bit and carry in bit and produces result of sum [3:0] and carry out which is acting as mux selection line for the next group, similarly the procedure continues for higher groups but they includes BEC logic instead of RCA with Cin=1.Based on the consideration of delay values, the arrival time of selection input C1 of 10:5 mux is earlier than the sum of CLA and BEC. For remaining groups the selection input arrival is later than the CLA and BEC. Thus, the sum1 and c1 (output from mux) are depending on mux and results computed by CLA and BEC respectively. The sum4 depends on c1 and mux. For the remaining parts the arrival time of mux selection input is always greater than the arrival time of data inputs from the BEC s. Thus, the delay of the remaining MUX depends on the arrival time of mux selection input and the mux delay. This structure is similar to regular 16-bit SQRT CSLA, the only change is that, we replace RCA with Cin=1 among the two available RCAs in a group with a BEC. This BEC can perform the similar operation as that 754 Copyright Vandana Publications. All Rights Reserved.

3 V. PROPOSED METHOD Fig 4: Block Diagram 755 Copyright Vandana Publications. All Rights Reserved.

4 VI. RESULTS Table 1 The implemented design in this work has been simulated using Verilog-HDL (Modelsim). The adders (of various size 8, 16, 32, and 64 ) are designed and simulated using Modelsim. All the V files (Regular and modified) are also simulated in Modelsim and corresponding results are compared. After simulation the different size codes are synthesized using Xilinx ISE The simulated V files are imported into the synthesized tool and corresponding values of delay and area are noted. The synthesized reports contain area and delay values for different sized adders. The similar From the above it is clear that the delay decreases for 8-bit modified method when compared with regular method. Similarly the table also shows the comparison for the various 16, 32, and 64 bits. Thus the modified method decreases the area to a great extent. Applications 1. Multiplication of many fft signals. 2. used in many multimedia devices. 3. used in many higher bit multipliers for faster addition. 4. Also used in many dft signals calculations and in many electronic devices. VII. CONCLUSION A simple approach is proposed in this paper to reduce the area of regular CSLA by using CLA architecture. The reduced number of gates of this work offers the great advantage in the reduction of area and also the total power. The reduction in the number of gates is obtained by simply replacing the RCA with CLA and BEC in the structure. The reduced number of gates of this work offers the great advantage in the reduction of area, delay and also the total power. The compared results show that the modified CSLA has a slightly larger delay (only 3.76%), but the area and power of the 64-b modified CSLA are significantly reduced by 17.4% and 15.4% respectively. The power-delay product and also the areadelay product of the proposed design show a decrease for 16-, 32-, and 64-b sizes which indicates the success of the method and not a mere tradeoff of delay for power and 756 Copyright Vandana Publications. All Rights Reserved.

5 area. The modified CSLA architecture is therefore, low area, low power, simple and efficient for VLSI hardware implementation. It would be interesting to test the design of the modified 128-b regular CSLA by using CLA. Tools: Modelsim 6.3 for Debugging and Xilinx 14.3 for Synthesis and Hard Ware Implementation. REFERENCES [1] O. J. Bedrij, Carry-Select Adder, IRE transactions on Electronics Computers, vol.ec-11, pp , June1962. [2] B.Ramkumar, Harish M Kittur and P.Mahesh Kannan, ASIC implementation of Modified Faster Carry Save Adder, European Journal of Scientific Research, vol.42, pp.53-58, [3] T.Y. Ceiang and M.-J. Hsiao, Carry-Select Adder using single Ripple-Carry Adder, Electronics letters, vol.34, pp , October [4] Y. Kim and L.-S. Kim, 64-bit carry-select adder with reduced area, Electronics Letters, vol.37, issue 10, pp , May [5] J. M. Rabaey, Digital Integrated Circuits- A Design Perspective, New Jersey, Prentice-Hall, Adder, Electronics letters, vol.34, pp , October [6] Y. He, C. H. Chang, and J. Gu, An Area Efficient 64- bit Square root carry select adder for Low power Applications, in Proc IEEE Int. Symp. Circuits Syst.2005, vol. 4, pp [7] Akhilesh Tyagi, A Reduced Area Scheme for Carry- Select Adders, IEEE International Conference on Computer design, pp , Sept Copyright Vandana Publications. All Rights Reserved.