MR Interface Analysis including Chord Signaling Options

Transcription

1 MR Interface Analysis including Chord Signaling Options David R Stauffer Margaret Wang Johnston Andy Stewart Amin Shokrollahi Kandou Bus SA May 12, 2014 Kandou Bus, S.A 1

2 Contribution Number: OIF Working Group: Physical & Link Layer WG (Electrical Track) Title: MR Interface Analysis including Chord Signaling Options Source: David R Stauffer david@kandou.com Date: May 12, 2014 Abstract: This analysis compares signal integrity and power analysis results for various Chord Signaling codes in CEI-56G Medium Reach (MR) channel applications. Codes are compared to an NRZ baseline. Notice: This contribution has been created to assist the Optical Internetworking Forum (OIF). This document is offered to the OIF solely as a basis for discussion and is not a binding proposal on the companies listed as resources above. Each company in the source list, and the OIF, reserves the rights to at any time to add, amend, or withdraw statements contained herein. This Working Text represents work in progress by the OIF, and must not be construed as an official OIF Technical Report. Nothing in this document is in any way binding on the OIF or any of its members. The document is offered as a basis for discussion and communication, both within and without the OIF. For additional information contact: The Optical Internetworking Forum, Fremont Blvd., Suite 117, Fremont, CA phone info@oiforum.com Kandou Bus, S.A 2

3 Disclosure discloses that we own intellectual property related to Chord Signaling and other material described in this contribution. We are committed to RAND licensing of all of our technologies. We are committed to adhering to the bylaws of all standards organizations to which we contribute and maintain membership. We are committed to be good corporate citizens. Kandou Bus, S.A 3

4 CEI Medium Reach Application Application is defined as 500 mm reach one connector CEI-28G-MR Insertion Loss: approx. 20 GHz. 4

5 Channel Requirements Project Start states requirement that max loss is in the range of: 15 to 25 db at 14 GHz 20 to 50 db at 28 GHz This allows the project to pick a wide range of possible insertion loss equations; some are worse than current CEI- 28G-MR and CEI-28G-LR channels. This contribution: Projects three possible equations for channel insertion loss; Compares signaling options (NRZ, PAM-4, ENRZ) for each of these channel options; and Provides power analysis comparing NRZ and ENRZ signaling. Kandou Bus, S.A 5

6 Basic CEI Insertion Loss Equation: CEI Channel Equation IIIIIIIIII = CEI-28G-MR: ccc + ccc ff ff bbbbbbbb ff bb ccc + ccc ff ff bbbbbbbb ff bb + ccc ff ff bbbbbbbb ff bb ff mmmmmm ff < ff bb 2 ff bb 2 ff ff bb f bmax = 28.1, c1 = 1.083, c2 = 2.436, c3 = 0.698, c4 = , c5 = CEI-28G-LR: f bmax = 25.8, c1 = 1.083, c2 = 3.35, c3 = 0.96, c4 = -9.25, c5 = Kandou Bus, S.A 6

7 Channel Options Channel options generated using: f bmax = 56.2 c1 = (same as CEI-28G-LR/MR) c2 = adjusted to produce desired loss c3 = c1 / (to match CEI-28G-LR/MR slope) c4 = calculated to avoid discontinuity at f b /2 c5 = (same as CEI-28G-LR/MR) Channel options: Option 3: Extends CEI-28G-MR channel (c2 = 2.436) Option 2: Extends CEI-28G-LR channel (c2 = 3.35) Option 1: Set for 50 db GHz (c2 = 3.663) Kandou Bus, S.A 7

8 Channel Options 8

9 Channel Models and Simulation Conditions SDD21 for NRZ / PAM-4 shown in top figure. SDD21 for ENRZ including all subchannels in bottom figure. Channel Models were constructed by concatenating: Package Model (5.4 mm) Daughter card PCB (5 inches) o FR4 (er=3.7, tand=0.019) Backplane connector (FCI) PCB trace (8, 13, or 15 inches) o FR4 (er=3.7, tand=0.019) Package Model (5.4 mm) Simulation Conditions: Tx Launch: 1000 mvppd 3-tap FFE, CTLE, 20-tap DFE No random jitter. Pass/Fail: 25 mvppd, 0.25 UI eye BER 1E-15 w/o FEC or 1E-6 w/fec. 9

10 Channel # GHz Channel # GHz Channel # GHz KEYE Results - NRZ Simulation conditions: GBd Tx Launch: 1000 mvppd FFE (3-tap) CTLE (0 to 12 db) DFE (20-tap) BER = 1E-6 (assumes FEC) Results: Pass/fail criteria: o o > 25 mvppd eye height > 0.25 UI eye width Case 3 eye is open. Case 1 & 2 eyes are closed. 10

11 Channel # GHz Channel # GHz Channel # GHz KEYE Results PAM4 Simulation conditions: GBd Tx Launch: 1000 mvppd FFE (3-tap) CTLE (0 to 12 db) DFE (20-tap) BER = 1E-6 (assumes FEC) Results: Pass/fail criteria: o o > 25 mvppd eye height > 0.25 UI eye width Case 3 eyes are open. Case 1 & 2 eyes are closed. 11

12 Channel # GHz Channel # GHz Channel # GHz KEYE Results ENRZ Simulation conditions: GBd Tx Launch: 1000 mvppd FFE (3-tap) CTLE (0 to 12 db) DFE (20-tap) BER = 1E-6 (assumes FEC) Results: Pass/fail criteria: o o > 25 mvppd eye height > 0.25 UI eye width Case 1 & 2 & 3 eyes are open. Sub-channel #2 eyes are shown at left (worst case). Sub-channel #1, #3 eyes are slightly better. 12

13 KEYE Results ENRZ w/o FEC SC#0 SC#1 Channel #3, 1e-15 SC#2 Simulation conditions: GBd Tx Launch: 1000 mvppd FFE (3-tap) CTLE (0 to 12 db) DFE (20-tap) BER = 1E-15 (no FEC) Results: Pass/fail criteria: o > 25 mvppd eye height o > 0.25 UI eye width Case 3 eyes are open. ENRZ will work w/o FEC on this channel. 13

14 KEYE Results - Detail Channel #1: Pkg (5.4mm) + 5in PCB + FCI conn. + 15in PCB + Pkg (5.4mm) Channel #2: Pkg (5.4mm) + 5in PCB + FCI conn. + 13in PCB + Pkg (5.4mm) Channel #3: Pkg (5.4mm) + 5in PCB + FCI conn. + 8in PCB + Pkg (5.4mm) 14

15 KEYE Results - Observations Results are consistent with prior published data: NRZ has open eyes for channel losses up to 30dB. NRZ operation can be extended up to 36 db using FEC. PAM-4 simulations tend to show similar results to NRZ for equivalent channels and signal processing. o Advantage of lower channel loss at lower baud rate is offset by lower launch amplitude. ENRZ performance tends to be better because: ENRZ takes advantage of correlation across 4 wires (not just 2 wires). Baud rate is lower than NRZ; less channel loss. ENRZ eye height is twice that of PAM-4. Kandou Bus, S.A 15

16 How Does Coding Save Power? Chord codes have the potential to save power: Less clocking power: CDR can be shared across wires. This increases number of transitions available, reducing run length constraints on the CDR, and amortizing circuit size/power across more than one bit stream. Lower equalization power: o Lower baud rate = less attenuation = less equalization required. o Better ISI tolerance can be achieved through proper code design. Lower Driver Power: Code design can reduce termination line power. This contribution analyzes ENRZ power consumption for a reference architecture relative to an NRZ implementation using an equivalent architecture. Kandou Bus, S.A 16

17 Power Analysis Methodology Purpose: Benchmark power of an ENRZ reference design to an equivalent NRZ reference design. Methodology applied: Kandou Wasp chip used as reference design for Serdes circuit and logic blocks (TSMC 28 nm, 28 GBd). Spice simulations used to determine power for circuit blocks of the reference design. Logic block power estimated based on synthesis results. Determine rules for scaling each block to other frequencies. Scale baseline power of each block to TSMC 16 nm process. Equivalent circuit architecture assumptions are used for all codes at all baud rates. (This avoids biasing results with architecture choices.) Benchmark: NRZ is used as a benchmark for the analysis methodology. This can be compared to power of existing examples of CEI-25G-LR Serdes products. Kandou Bus, S.A 17

18 NRZ Power Estimate (CEI-25G-LR Baseline) Baseline configuration: 112 Gb/s interface NRZ signaling 4 GBd CEI-25G-LR compliant TSMC 28 nm process DFE: 12-tap Typical power: pj/bit Calculation is comparable to examples of CEI-25G-LR Serdes known to the author. CDR, Rx Analog, Power Breakdown (mw) DFE, Tx Analog, Clock Dist., Digital Logic, Power Total (mw) Data Throughput (Gb/s) Energy per Bit (pj/bit) PLL, Termination,

19 NRZ Power Estimate (CEI-56G-MR) Baseline configuration: 112 Gb/s interface NRZ - 2 Gb/s TSMC 16 nm process DFE: 20 tap FEC required but not included in power budget. Typical power: 9.88 pj/bit Analysis shows 16% power reduction for next generation. Power advantage of next process node is offset by higher baud rate. Power is not scaling by 30% as has been the case for prior generations of NRZ Serdes. Industry requires larger power reductions than past generations. Rx Analog, Power Breakdown (mw) CDR, DFE, Tx Analog, Clock Dist., Digital Logic, Power Total (mw) Data Throughput (Gb/s) Energy per Bit (pj/bit) 9.88 PLL, Termination,

20 ENRZ Power Estimate (CEI-56G-MR) Baseline configuration: 112 Gb/s interface ENRZ - 1 Gb/s TSMC 16 nm process DFE: 20 tap FEC not included requirement depends on baseline. Typical power: 6.79 pj/bit Analysis shows 42% power reduction for next generation. Baud rate scales more in line with process transistor speeds. Power reduction is exceeds 30% scaling typical of prior generations. CDR, Rx Analog, Power Breakdown (mw) DFE, Clock Dist., Tx Analog, Digital Logic, Power Total (mw) Data Throughput (Gb/s) Energy per Bit (pj/bit) 6.79 PLL, Termination,

21 Summary Three channels were analyzed with various insertion losses consistent with the ranges in the project start. Only the best of these channels had open eyes for NRZ or PAM-4 signaling simulations. o FEC was required in both cases. ENRZ eyes were open for all channels. o FEC was only required for the two higher loss channels. NRZ and ENRZ power was analyzed: NRZ power is not scaling at the same rate as prior generations. ENRZ offers significant power savings over an NRZ implementation. Target of 6.79 pj/bit is projected for ENRZ. Analysis demonstrates advantage of ENRZ over NRZ: CEI-56G-MR channel can be defined for a higher insertion loss than can be supported for other signaling methods. Substantial power savings are possible. Kandou Bus, S.A 21

22 KANDOU reinventing the BUS Kandou Bus, S.A 22