Maintenance/ Discontinued

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1 CCD Delay ine Series MN38663S NTSC-Compatible CCD Video Delay Element Overview The MN38663S is a CCD signal delay element for video signal processing applications. It contains such components as a threefold-frequency circuit, a clock driver, charge I/O s, two CCD s switchable between and 605 stages, a clamp bias circuit, resampling output amplifiers, and booster circuits. When the switch is "" level, the MN38663S samples the using the supplied clock signal with a frequency of three times the NTSC color signal subcarrier frequency ( Mz) and, after adding in the attached filter delay, produces independent delays of 1 (the horizontal scan period) each for the two lines. When the switch is "" level, the MN38663S disables the threefold-frequency circuit and samples the with the image sensor drive frequency ( Mz) for the camera's 510 horizontal pixels and, after adding in the attached filter delay, produces independent delays of 1 (the horizontal scan period) each for the two lines. Features Single 4.4 V power supply Choice of camera and VCR modes, so that both the camera and VCR portions of a video camera with 510 horizontal pixels can use the same MN38663S for signal processing Applications Video cameras Pin Assignment XIC V SS3 V DD3 VINC1 N.C. VINVC VGC1 VO1C V DD1 V SS1 ( TOP VIEW ) SOP020-P XIV PCOUT & VCOIN V BB V SS2 V DD2 VINVY SW VINC2 VGC2 VO2Y includes following four Product lifecycle stage. SDB00072BEM 1

2 MN38663S CCD Delay ine Series Block Diagram V DD1 V SS1 V DD2 V SS2 V DD3 V SS3 SW VGC1 VGC2 VINVC 6 4 VINC1 15 VINVY 13 VINC2 XIV 20 XIC 1 Bias circuit Waveform amplifier Phase comparator 19 PCOUT & VCOIN Clamp circuit 1/3rd frequency divider VCO 78.5-stage 3-stage 78.5-stage 3-stage Mode switch Waveform Timing 602-stage V SS 602-stage Booster circuit ø1 driver ø2 driver detector detector Voltage generator Voltage generator Resampling output amplifier Resampling output amplifier øs driver ør driver øs driver Substrate bias generator 18 V BB 8 11 VO1C VO2Y includes following four Product lifecycle stage. 2

3 CCD Delay ine Series MN38663S Pin Descriptions Pin No. Symbol Pin Name Function Description 1 XIC Mz clock 2 V SS3 GND (3) Ground for clock multiplier circuit 3 V DD3 Power supply (3) Power supply for clock 4 VINC1 Camera signal (1) 5 N.C. No connection 6 VINVC Video signal (C) multiplier circuit 7 VGC1 Output gate connection (1) 8 VO1C output (1C) Output pin for signal fed to pin 4 or pin 6 9 V DD1 Power supply (1) Power supply for circuits 10 V SS1 GND (1) Ground for circuits 11 VO2Y output (2Y) Output pin for signal fed to pin 13 or pin VGC2 Output gate connection (2) 13 VINC2 Power supply (2) 14 SW Camera/video mode switch 15 VINVY Video signal (Y) 16 V DD2 Power supply (2) Power supply for digital circuits other than frequency multiplier 17 V SS2 GND (2) Ground for digital circuits other than frequency multiplier 18 V BB Substrate connection Negative voltage pin 19 PCOUT&VCOIN Phase comparator output and voltage controlled oscillator 20 XIV Mz clock Notes 1: Always connect V DD1, V DD2, and V DD3 to the same voltage. 2: Always connect V SS1, V SS2, and V SS3 to ground. includes following four Product lifecycle stage. 3

4 MN38663S CCD Delay ine Series Electrical Characteristics V DD =4.4V, V ckv =0.3V P-P (sine wave), f ckv = Mz (Converted to Mz internally) V ckc =0.3V P-P (sine wave), f ckc = Mz, V in =0.5V P-P (sine wave), Ta=25 C Parameter Symbol Conditions min typ max Unit Power supply current Average current for 4.4-V power I DDV (Video signal I/O) supply when SW is "" level ma Power supply current Average current for 4.4-V power I DDC (Camera signal I/O) supply when SW is "" level bandwidth (Video signal I/O) bandwidth (Camera signal I/O) BWV BWC 3 db for 200 kz value when SW is "" level 3 db for 200 kz value when SW is "" level Insertion gain IG f sig =200kz db Total harmonic distortion TD f sig =200kz 1 4 % -to-noise ratio S/N output (V P-P )/noise output (rms) db Clock leak (V1) Clock leak (C) Clock leak (V2) NCV1 NCC NCV Mz component output/main output signal when SW is "" level Mz component output/main output signal when SW is "" level Mz db db Mz component output/main db output signal when switch signal is "" level Crosstalk CT f sig =200kz 37 db Delay (Video signal I/O) τ DV When SW is "" level Delay (Camera signal I/O) τ DC When SW is "" level VO pin output impedance ZO Ω Input bias voltage V BINC Applicable to signal pins VINC1 and VINC2 µs V Input bias voltage V BINY Applicable to signal pin VINC V Input clamp voltage V CIN Applicable to signal pin VINVY V Output bias voltage V BOC Applicable to signal output pins VO1C V and VO2Y when SW is "" level Applicable to signal output pin Output bias voltage V BOY VO1C when SW is "" level Applicable to signal output pin Output clamp voltage V CO VO2Y when SW is "" level V V Substrate voltage V BB 2.5 V includes following four Product lifecycle stage. 4

5 CCD Delay ine Series MN38663S Application Circuit Example + 4.4V 10m 4.4V or GND 0.01µF 0.01µF 0.1µF 0.1µF 0.1µF V DD1 V SS1 V DD2 V SS2 V DD3 V SS3 SW VGC1 VGC2 VINVC µF VINC µF VINVY µF + VINC µF + Clock XIV 20 Clock 1000pF 1000pF XIC 1 Bias circuit Waveform amplifier Phase comparator 19 PCOUT & VCOIN Clamp circuit 1/3rd frequency divider VCO 78.5-stage 3-stage 78.5-stage 3-stage Mode switch 602-stage 602-stage Waveform Timing Booster circuit ø1 driver detector detector Voltage generator Voltage generator Resampling output amplifier Resampling output amplifier øs driver ør driver ø2 driver øs driver Substrate bias generator 18 V BB 0.01µF 8 VO1C output (1C) 11 VO2Y output (2Y) includes following four Product lifecycle stage. 0.01µF 820Ω 1000pF Note: If the capacitor attached to pin 18 has a polarity, attach the negative pole to pin 18. 5

6 MN38663S CCD Delay ine Series Package Dimensions (Unit:mm) SOP020 P ± (0.6) ±0.1 Seating plane 5.5± ± ± max. 7.7± ± min. Note) The package of this product will be changed to the following lead-free type (SOP020-P-0300D). includes following four Product lifecycle stage

7 CCD Delay ine Series MN38663S New Package Dimensions (Unit: mm) SOP020-P-0300D (ead-free package) ± ± (0.60) 1.27 Seating plane ± ± ± ± max min. 0 to 10 Seating plane includes following four Product lifecycle stage. 7

8 Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products, and no license is granted under any intellectual property right or other right owned by our company or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. Any applications other than the standard applications intended. (4) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., td. includes following four Product lifecycle stage.

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