Prepare for Next Generation USB Technology Testing

Transcription

1 Prepare for Next Generation USB Technology Testing

2 Disclaimer The USB 3.1 compliance test requirements are not final therefore all opinions, judgments, recommendations, etc., that are presented herein are the opinions of the presenter of the material and do not necessarily reflect the opinions of USB-IF or other member companies.

3 Agenda USB updates Introduction to USB 3.1 What s different Type-C Connector Power Delivery (PD) Transmitter Test Receiver Test Summary Q&A

4 USB in the News > 1000 USB 3.0 products certified including many hubs Almost 1 billion shipped in 2013 USB 3.1 updated specification released (August 2014) NEW Type-C connector Power Delivery 2.0 (PD) ECNs including electrical and link layer changes Source:

5 Increasing Serial Data Bandwidth USB 2.0, 480 Mb/s (2000) Shift from slower, wide, parallel buses to narrow, high speed serial bus 40x faster data rate, support for new connectors & charging USB 3.0, 5 Gb/s (2008) ~10x faster data rate over 3 meter cable Faster edges, closed eye architecture USB 3.1, 5/10 Gb/s (2013) 2x faster data rate over 1 meter cable Scaled SuperSpeed implementation High Speed USB Cable SuperSpeed USB Cable

6 Evolution of the USB3 Connector Standard A Plug (2008) ~5000 insertions 900mA Micro B Plug (2008) ~10,000 insertions 900mA USB Type-C Plug (2014) ~10,000 insertions 5A* Reversible Orientation

7 Type-C Comparison Rounded, reversible, flip-able ~25% less width vs.µb Signaling Two SS differential pairs Vbus power Configuration Channel (CC) USB 2.0 differential pair Sideband Use (SBU) Plug power (Vconn) Micro B Plug Type-C Plug * New signals

8 Plug Up Orientation USB Type-C Upside Up Note, end-to-end signaling have swapped pairs (e.g. Host_A2 ( TX1+ ) Device_A11 ( RX2+ ) )

9 Plug Down Orientation USB Type-C Upside Down (both plugs flipped) Note, end-to-end signaling have swapped pairs (e.g. Host_A2 ( TX1+ ) Device_A11 ( RX2+ ) )

10 USB Power USB 3.0 power handling -> Up to 900 ma (Nov 2008) Battery Charging (BC 1.2, Dec 2010) Increases charging of up to 1.5 A No simultaneous data transfer in high power mode Wall Power Power Delivery (PD 2.0, August 2014) specification Up to 100W with switchable power delivery source Switchable power delivery source without changing cable direction Consumer Provider Consumer Provider Consumer Consumer Self Power

11 Emulating a Device or Consumer Control PC USB 3.0 Upload Host or Provider Analyzer Generator (Device or Consumer) * Using EX350 analyzer/generator. Images courtesy of Ellisys

12 Consumer/Provide Role Swap Example * Using EX350 analyzer/generator. Images courtesy of Ellisys

13 PD Physical Layer Testing Type--C PD Electrical Testing BMC Signaling Similar to Manchester Encoding

14 Test Setup (Provider/Consumer Example) 14 USB-PD Coupon(s) Passive Probe API? Ellisys EX-350

15 GRL-USB-PD Required Equipment for PD Testing Tektronix Oscilloscope DPO5000 Series and above GRL-USB-PD Power Delivery SW 2ea. Passive Probes for CC and VBUS 1ea. Current Probe for Load Current USB-PD Coupons USB3.1-C-PDC from Wilder-Tech USB-PD Controller and Protocol Generator EX-350 from Ellisys TCP-2020A Download Data Sheet and Demo SW amazonaws.com/grl.ap.public.download/GRL+Test+Solutions/Datasheets/GRL- USB-PD_Tek_datasheet.pdf

16 Electrical Validation of SuperSpeed USB 10 Gb/s

17 Interoperability Challenge Goal: Any certified host works with any certified hub or device Short Channel 1" host PCB route ¼ " device PCB route Direct plug Long channel 4" host PCB route 4" device PCB route 1m cable Source: USB-IF

18 USB 3.1 Comparison Gen1 Gen2 Data Rate 5 Gb/s 10 Gb/s Encoding 8b/10b 128b/132b Target Channel 3m + Host/Device channels (-17dB, 2.5 GHz) 1m + board ref channels (-23dB, 5 GHz) LTSSM LFPS, TSEQ, TS1, TS2 LFPSPlus, SCD, TSEQ, TS1, TS2, Reference Tx EQ De-emphasis 3-tap (Preshoot/De-emphasis) Reference Rx EQ CTLE CTLE + 1-tap DFE JTF Bandwidth 4.9 MHz 7.5 MHz Eye Height (TP1) 100 mv 70 mv TJ@BER 132 ps (0.66 UI) 71 ps (0.714 UI) Backwards Compatibility Y Y Connector Std A Improved Std A with insertion detect 3/ Tektronix 55W

19 128b/132b Encoding and Compliance Patterns 4-bit block header (0011 control, 1100 data) 128-bit (16 bytes) non-encoded payload Similar to PCI Express but with 4-bit header 1 bit error (self correcting) 2 bit error (detection) SKP Ordered Set Clock compensation (+300 to -5300ppm offset) Dynamically inserted/removed Includes LFSR state (good for test equipment) Higher order scrambler (X 23 vs. X 16 ) Improves EQ training with long, rich pattern Compliance with scrambled data (00h) and Nyquist (Ah) Pattern toggle between Gen1 and Gen2 3/ Tektronix 55W

20 New Channel Budget* Target 23 5 GHz loss budget (die-to-die) Equal channel allocation for host/device Tx EQ settings (normative) 2.2 db Preshoot and -3.1 db De-emphasis Requires additional compliance patterns for Tx testing Host or device loss that exceeds 8.5 db may required repeater Need end-to-end training -> link aware repeaters 8.5 db 6 db 8.5 db * Items in red indicate new as Aug 2014 release 3/ Tektronix 55W

21 USB 3.1 Transmitter Measurement Overview Spec Reference Table 6-16 Table 6-17 Table 6-17 Table 6-18 Table 6-19 Table 6-28 Table 6-29 Table 6-31 Table 6-32 Parameter SSC Modulation Rate SSC Deviation Unit Interval including SSC Maximum Slew Rate (5 GT/s) SSC df/dt (10 GT/s) Differential p-p Tx Voltage Swing Low-power Differential p-p Tx Voltage Swing De-emphasized Output Voltage Ratio (5 GT/s) Tx Min Pulse Deterministic Min Pulse Transmitter DC Common Mode Voltage Tx AC Common Mode Voltage Active Transmitter Eye RJ/DJ/TJ - Dual Dirac at BER LFPS Common Mode Voltage LFPS Differential Voltage LFPS Rise Time LFPS Fall Time LFPS Duty Cycle LFPS tperiod LFPS tperiod-ssp (10 GT/s) LFPS tburst LFPS trepeat LFPS trepeat-0 (10 GT/s) LFPS trepeat-1 (10 GT/s) LFPS Pulse Width Modulation (10 GT/s) tlfps-0 (10 GT/s) tlfps-1 (10 GT/s) 12/11 3/ Tektronix 55W W Clock (CP10) PHY (CP9) LFPS

22 SuperSpeed Transmitter Compliance Testing 1. Connect DUT to scope via test fixture 2. Transmit CP10 (clock) & measure 10 6 consecutive UI This step used to measure RJ 1. Repeat with CP9 (scrambled data pattern) Will combine RJ (step 2) with DJ to extrapolate TJ (step5) 1. Post-process the waveforms with the compliance channel, the reference CTLE, & jitter transfer function Channels are S-Parameter-based and are embedded into captured waveform 1. Extrapolate jitter to BER Spec Min Max Units Eye Height mv BER 0.53 UI BER UI BER UI 3/ Tektronix 55W

23 Example Host Test Setup SMA cable to scope Ping.LFPS from signal generator (pattern toggle) Host Short USB cable *Note, Gen1 setup shown for illustration only 3/ Tektronix 55W

24 Transmitter Capture and Channel Embed Capture CP9 (data) and CP10 (clock) Input reference channel models Reference Channel CP9 Scrambled Pattern (TP0) CP9 Scrambled Pattern (TP1) 3/ Tektronix 55W

25 Reference Receiver Equalizer Far End (TP1) Eye closed Need to open eye with EQ Adaptation only for Rx No back channel Tx negotiation Iterate through multiple CTLE gain settings + 1-tap DFE 3/ Tektronix 55W

26 Transmitter Validation Example Find optimum Eye height vs. Rx EQ 63 mv - Fail 60 mv - Fail 103 mv - Pass 3/ Tektronix 55W

27 USB 3.1 Recommended Transmitter Solution 20 GHz BW, 100 GS/sec preferred >10M minimum record length allows capture of 1M UI at 100 GS/sec, no interpolation. DPOJET for advanced jitter/eye analysis SDLA for channel embedding and cycling through 7 CTLE/1 DFE settings TekExpress automation software for USB 3.1 gen1/gen2 physical layer validation For instrument bandwidth, consider factors such as: Edge Rate Reflections SNR (de-embedding) Launch Characteristics 3/ Tektronix 55W

28 USB 3.1 Receiver Testing Overview A jitter tolerance test is required for certification, though: Debug and characterization capabilities are needed to ensure that receivers will work in real world conditions: Send specific test data patterns to the device-under-test (DUT) through a known channel (fixtures and cables) Add a specific recipe of stresses and de-emphasis Command the DUT into loopback mode (far-end retimed) Return echoed data to a BERT Detected errors are inferred to be a result of bad DUT receiver decisions Complete Link Transmitter Receiver Channel 12/11 3/ Tektronix 55W W

29 Polling Sub-states Successful Gen2 link training with loopback asserted Enter in Loopback mode No link partner response Enter Tx compliance mode Training failure Retry at Gen1 rate LFPS detected but no LFPSPlus - Train at Gen1 rate 3/ Tektronix 55W

30 Link Training Updates (ECNs) for Rx Testing TSEQ default changes to 524,288 ordered sets (Polling.RxEQ) Previous length was 262,143 Longer repeat length for testing many coefficient settings USB 3.1 Gen2 Receiver architecture Pattern generator to send 24-symbol skip ordered sets instead of 16-symbol skip ordered sets. Relaxes buffer requirements for systems with retimers Affects link training as well as Rx compliance pattern 3/ Tektronix 55W

31 JTOL Template Comparison Symbol Parameter Gen 1 Gen 2 Units Notes f1 Tolerance corner MHz J Rj Random Jitter UI rms 1 J Rj_p-p Random Jitter peak- peak at UI p-p 1,4 J Pj_500kHz Sinusoidal Jitter UI p-p 1,2,3 J Pj_1Mhz Sinusoidal Jitter UI p-p 1,2,3 J Pj_2MHz Sinusoidal Jitter UI p-p 1,2,3 J Pj_4MHz Sinusoidal Jitter N/A 0.37 UI p-p 1,2,3 J Pj_f1 Sinusoidal Jitter UI p-p 1,2,3 J Pj_50MHz Sinusoidal Jitter UI p-p 1,2,3 J Pj_100MHz Sinusoidal Jitter N/A 0.17 UI p-p 1,2,3 V_full_swing Transition bit differential voltage swing V p-p 1 V_EQ_level Non transition bit voltage (equalization) -3 Pre=2.2 Post= -3.1 db 1 Notes: 1. All parameters measured at TP1. The test point is shown in Figure Due to time limitations at compliance testing, only a subset of frequencies can be tested. However, the Rx is required to tolerate Pj at all frequencies between the compliance test points. 3. During the Rx tolerance test, SSC is generated by test equipment and present at all times. Each J Pj source is then added and tested to the specification limit one at a time. 4. Random jitter is also present during the Rx tolerance test, though it is not shown in Figure /11 The JTOL 2011 Tektronix specs for Gen 55W comprehend jitter peaking with re-timers in the system and has a 25 db/decade slope.

32 Receiver Tolerance Test Overview Seven Test Points SSC Clocking is enabled BER Test is performed at Preshoot/De-emphasis enabled Stress verified by Eye Height and Width Each SJ term in the table below is tested one at a time after the device is in loopback mode Frequency SJ RJ 500kHz 476ps 1.0ps RMS 1MHz 203ps 1.0ps RMS 2MHz 87ps 1.0ps RMS 4MHz 37ps 1.0ps RMS 7.5MHz 17ps 1.0ps RMS 50MHz 17ps 1.0ps RMS 100MHz 17ps 1.0ps RMS 12/11 3/ Tektronix 55W W

33 Generic RX Test Configuration 12/ Tektronix 55W

34 Stress Recipe - Calibration Tx Eq Long waveform capture by Real Time Scope PRBS Gen Channel Test Equipment RJ Source SJ Source SigTest Postprocessing Mature standard with fully automated solutions for stress calibration and good correlation

35 BERTScope USB RX Test Configuration USB Switch Creates the low-frequency periodic signaling (LFPS) required to initiate Loopback-mode DPP125C De-emphasis Processor CR125A Clock Recovery BSA125C BERTScope 3/ Tektronix 55W

36 Summary Higher performance with SuperSpeed USB 10 Gb/s and better user experience with USB Type-C connector and Power Delivery USB 3.1 adds additional challenges beyond legacy requirements (backwards compatibility) Tektronix extensive PHY validation tools for early designs USBSSP automation for Tx validation BERTScope USB library with JTOL templates Automated calibration, loopback entry and JTOL simplifies overall testing 10/2014 Tektronix 55W / Tektronix 55W