Flip-flop and Registers

Transcription

1 ECE 322 Digital Design with VHDL Flip-flop and Registers Lecture

2 Textbook References n Sequential Logic Review Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 2 nd or 3 rd Edition Chapter 7 Flip-flop, Registers, Counters, and a Simple Processor n In this lecture, we learn how to implement basic sequential blocks using VHDL Latches Flip-flop Registers

3 Sequential Circuits n In a combinational circuit, the output depends only on the circuit s inputs. n In a sequential circuit, the output depends not only on the circuit s inputs, but also on the values of a subset of the circuit s nodes (which can include the output) which are fed back into the circuit. This set of feedback node values is called the State (S) Y Y = = f( X) f( X, S) combinational sequential

4 Sequential Circuits Why are sequential circuits called sequential? n It is because the circuit s state depends on the input values from past times. n This behavior causes a time sequence of output values to arise which depends on the time sequence of the input values.

5 A Simple Memory Element This circuit has two possible states: n A = B = n A = B = A B A simple memory element

6 Sequential Circuits-SR Latch Consider a more complicated circuit the SR latch created by cross-coupling two NOR gates. (NAND gates could also be used). R a S b The circuit state includes the signals a and b as these are the signals that are fed back into the circuit.

7 Sequential Circuits-SR Latch R S a b S R a b / / (no change) (a) Circuit (b) Truth table t t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t R S a b?? (c) Timing diagram Time

8 Sequential Circuits-Gated D Latch Graphical symbol D Truth table D (t+) (t) Timing diagram D t t 2 t 3 t 4 Time

9 VHDL Code for Gated D Latch LIBRARY ieee ; USE ieee.std_logic_64.all ; ENTITY latch IS PORT ( D, : IN STD_LOGIC ; : OUT STD_LOGIC) ; END latch ; ARCHITECTURE behavioral OF latch IS BEGIN PROCESS ( D, ) BEGIN IF = '' THEN <= D ; END IF ; END PROCESS ; END behavioral; D

10 Sequential Circuits There are two main ways of synchronizing sequential circuits: Level-sensitive ing or Gating Edge-triggered ing The level of a gate signal specifies whether the non-gate inputs to the circuit will affect the outputs. When the gate is at its active level, the inputs will be continually active. In edge-triggered clocking, the inputs will only affect the outputs when the clock signal is transiting from low to high (or from high to low, or perhaps in both directions).

11 Master-Slave D Flip-Flop One straightforward approach to creating an edge-triggered synchronous circuit is to combine two gated D latches, one after the other, with their gate signals inverted relative to each other. This produces the so-called Master-Slave D Flip-Flop.

12 Master-Slave Flip-Flop Gated D-latches

13 Positive-edge-triggered D Flip-Flop Graphical symbol D Truth table Clk D (t+) (t) (t) Timing diagram D t t 2 t 3 t 4 Time

14 VHDL Code for Positive-edge-triggered D Flip-Flop LIBRARY ieee ; USE ieee.std_logic_64.all ; ENTITY flipflop IS PORT ( D, : IN STD_LOGIC ; : OUT STD_LOGIC) ; END flipflop ; D ARCHITECTURE behavioral OF flipflop IS BEGIN PROCESS ( ) BEGIN IF 'EVENT AND = '' THEN <= D ; END IF ; END PROCESS ; END behavioral ;

15 VHDL Code for Positive-edge-triggered D Flip-Flop LIBRARY ieee ; USE ieee.std_logic_64.all ; ENTITY flipflop IS PORT ( D, : IN STD_LOGIC ; : OUT STD_LOGIC) ; END flipflop ; D ARCHITECTURE behavioral2 OF flipflop IS BEGIN PROCESS ( ) BEGIN IF rising_edge() THEN <= D ; END IF ; END PROCESS ; END behavioral2;

16 VHDL Code for a D Flip-Flop with Asynchronous Reset LIBRARY ieee ; USE ieee.std_logic_64.all ; ENTITY flipflop_ar IS PORT ( D, Resetn, : IN STD_LOGIC ; : OUT STD_LOGIC) ; END flipflop_ar ; D Resetn ARCHITECTURE behavioral OF flipflop_ar IS BEGIN PROCESS ( Resetn, ) BEGIN IF Resetn = '' THEN <= '' ; ELSIF rising_edge() THEN <= D ; END IF ; END PROCESS ; END behavioral ;

17 VHDL Code for a D Flip-Flop with Synchronous Reset LIBRARY ieee ; USE ieee.std_logic_64.all ; ENTITY flipflop_sr IS PORT ( D, Resetn, : IN STD_LOGIC ; : OUT STD_LOGIC) ; END flipflop_sr ; ARCHITECTURE behavioral OF flipflop_sr IS BEGIN PROCESS() BEGIN IF rising_edge() THEN IF Resetn = '' THEN <= '' ; ELSE <= D ; END IF ; END IF; END PROCESS ; END behavioral ; D Resetn

18 Asynchronous vs. Synchronous n In the IF loop, asynchronous items are Before the rising_edge() statement n In the IF loop, synchronous items are After the rising_edge() statement

19 Different types of flip-flops can be constructed by adding circuitry to the basic D flip-flop.

20 T Flip-Flop D T T ( t + ) t ( ) T t ( ) (a) Circuit (b) Truth table (c) Graphical symbol T (d) Timing diagram

21 J-K Flip-Flop J D K (a) Circuit J K (t +) ( t ) (t ) (b) Truth table J K (c) Graphical symbol

22 Registers

23 Register A flip-flop stores one bit of information. When a set of n flipflops is used to store n bits of information, we refer to these flip-flops as a register. A common clock is used for each flip-flop in a register

24 Shift Register In D D D D Out Clk In Clk SHIFT REGISTER Out t In (a) Circuit = Out t t 2 t 3 t 4 t 5 t 6 t 7 (b) A sample sequence

25 Parallel-Access Shift Register Parallel output 3 2 D D D D clock serial_in parallel_in 4 SHIFT REGISTER 4 output shift/load Serial input Shift/Load Parallel input

26 VHDL Code for a 8-Bit Register with Asynchronous Clear LIBRARY ieee ; USE ieee.std_logic_64.all ; ENTITY reg8 IS PORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO ) ; Resetn, : IN STD_LOGIC ; : OUT STD_LOGIC_VECTOR(7 DOWNTO ) ) ; END reg8 ; ARCHITECTURE behavioral OF reg8 IS BEGIN PROCESS ( Resetn, ) BEGIN IF Resetn = '' THEN <= "" ; ELSIF rising_edge() THEN <= D ; END IF ; END PROCESS ; END behavioral ;` 8 Resetn 8 D reg8

27 Use of GENERIC in VHDL n n n n Generics allow a design entity to be described so that, for each use of that component, Its structure and behavior can be changed by generic values. In general they are used to construct parameterized hardware components. Generics are typically integer values Ø Ø In this class, the entity inputs and outputs should be std_logic or std_logic_vector But the generics can be integer Generics are given a default value Ø GENERIC ( N : INTEGER := 6 ) ; Ø This value can be overwritten when entity is instantiated as a component Generics are very useful when instantiating an often-used component Ø Ø Need a 32-bit register in one place, and 6-bit register in another Can use the same generic code, just configure them differently

28 Use of OTHERS in VHDL OTHERS stand for any index value that has not been previously mentioned. <= can be written as <= ( =>, OTHERS => ) <= can be written as <= (7 =>, =>, OTHERS => ) or <= (7 =>, OTHERS => ) <= can be written as <= (4 downto =>, OTHERS => )

29 VHDL Code for a N-Bit Register with Asynchronous Clear LIBRARY ieee ; USE ieee.std_logic_64.all ; ENTITY regn IS GENERIC ( N : INTEGER := 6 ) ; PORT ( D : IN STD_LOGIC_VECTOR(N- DOWNTO ) ; Resetn, : IN STD_LOGIC ; : OUT STD_LOGIC_VECTOR(N- DOWNTO ) ) ; END regn ; ARCHITECTURE behavioral OF regn IS BEGIN PROCESS ( Resetn, ) BEGIN IF Resetn = '' THEN <= (OTHERS => '') ; ELSIF rising_edge() THEN <= D ; END IF ; END PROCESS ; END behavioral ; N Resetn D regn N