ECT 224: Digital Computer Fundamentals Digital Circuit Simulation & Timing Analysis

Transcription

1 ECT 224: Digital Computer Fundamentals Digital Circuit Simulation & Timing Analysis 1) Start the Xilinx ISE application, open Start All Programs Xilinx ISE 9.1i Project Navigator or use the shortcut on the desktop ( ). 2) Open a project or create a new project (use the C:\ET224L directory) 3) Create a stimulus (waveform) file to exercise the digital design needing to be analyzed a) In the Sources window select the Behavioral Simulation option for the Sources for: category as shown in Figure 1. b) Right-click on the project name in the Sources window and select the option to New Source c) In the New Source Wizard window select the Test Bench Waveform option and provide a meaningful name for this waveform file (can be same as the project or schematic names, remember to not use spaces in names) as shown in Figure 2, and finally select the Next, Next (to associate it with the current project), and Finish options. Figure 1: "Sources" window setup to select behavioral simulation source Figure 2: New source window setup for adding a waveform

2 4) The test bench waveform editor is initialized from within the Initialize Timing and Clock Wizard window (should automatically pop-up). To setup for analysis of combinatorial circuits go to step 4a, for analysis of sequential circuits go to step 4b, and for analysis of sequential circuits with asynchronous inputs go to steps 4b and 4c. a) To setup a waveform for combinatorial logic: select the Combinatorial radio button under Clock Information, change the Check Inputs and Check Outputs to be 5ns instead of the default 50ns, and change the Initial Length of test bench value to 1000ns as shown in Figure 3. Finally select Finish and the test bench waveform file (*.tbw) will be generated and loaded within the Xilinx ISE. Do not worry if the window has a black box instead of the timing image shown in Figure 3. Figure 3: Timing setup for combinatorial circuit simulation b) To setup a waveform for synchronous logic, select the Single Clock radio button under Clock Information and change the Initial Length of Test Bench value to 1000 as shown in Figure 4. Be sure to set the valid edge of the clock and the associated clock information in the Clock Timing Information section. Finally select Finish and the test bench waveform file (*.tbw) will be generated and loaded within the Xilinx ISE. Figure 4: Timing setup for sequential circuit simulation using a single clock source

3 c) To setup a waveform that contains asynchronous inputs select the Add Asynchronous Signal Support option in the Initial Timing and Clock Wizard window (this will grey-out all clock options). Finally select Next and the Initial Timing and Clock Wizard Clock Selection window will open. i) Highlight the circuit s clock signal (make sure the Add Asynchronous Signal Support option is selected) and select Next as shown in Figure 5. Figure 5: Selecting the clock signal when using asynchronous inputs ii) Within the Initial Timing and Clock Wizard Clock and Signal Association window each I/O signal must be defined as either synchronous by being associated with the selected clock signal or defined as asynchronous by being associated with the Asynchronous Signal clock option. Figure 6 depicts how an input signal for a switch can be defined as asynchronous. Once all I/O signals have been associated, select Next. Figure 6: Defining all I/O signals as synchronous or asynchronous through their association

4 iii) Within the Initial Timing and Clock Wizard Clock Timing Setup window the clock timing parameters must be set including the valid edge of the clock as shown in Figure 7. Finally select Finish and the test bench waveform file (*.tbw) will be generated and loaded within the Xilinx ISE. Figure 7: Timing setup for simulation with asynchronous inputs 5) The input waveforms within the test bench waveform editor are modified by clicking on them wherever you want them to change state. The blue shaded areas indicate the time after which the outputs are valid, the input setup time (in our case 5ns). An input value for a particular location on the waveform can be set by double-clicking on the desired location and then entering the required binary value in the Set Value pop-up window as demonstrated in Figure 8. The Set Value pop-up window also contains a pattern wizard which allows the user to create a specified waveform pattern starting at the location the mouse was double-clicked. a) Note that for synchronous circuit simulations the output signals will not change until after the global-set-reset (GSR) pulse at the start of simulation which ends at roughly 100ns. b) Bus input waveforms can be entered by typing in their values using the desired notation (select decimal, hexadecimal, binary, or ASCII by right-clicking on waveform) as shown in Figure 9. The bus can also be expanded and each individual waveform can be updated independently. Figure 8: Using the Set Value window to specify the waveform format

5 Figure 9: Modifying bus values c) To zoom into the waveform use the button, to zoom out use the button, and to view the entire waveform use the button. d) To place markers onto the waveform to help read or setup the timing information use the, or buttons for a measure marker or a single marker, and then click and drag the markers to the desired locations. 6) Save the developed waveform file by pressing CTRL+S which will add the waveform file as a source to the project (shown in the Sources window ) and then close the test bench waveform editor window. 7) To create a self-checking test bench the output waveforms can be edited manually or automatically using the Generate Expected Results process. a) Highlight the new test bench waveform (*.tbw) file in the Sources tab within the Sources window. In the Processes window select the Processes tab and the Xilinx ISE Simulator category and right-click on the Simulate Behavioral Model option and run the synthesis, as shown in Figure 10. b) The simulation window will automatically open with the output values from the simulation. Figure 10: "Processes" window for simulating the behavioral model from the test bench

6 8) The ISE Simulator can be used with the developed test bench to perform a post-place and route simulation. Since the design has been mapped to the chip during the placeand route process, a more accurate simulation can be performed that will also provide timing information such as delays of the output signals a) In the Sources window select the Post-Route Simulation option for the Sources for: category. b) Highlight the test bench waveform file (*.tbw) under the Sources tab in the Sources window. c) Run the simulation by double-clicking on the Simulate Post-Place & Route Model from the Xilinx ISE Simulator option as shown in Figure 11. A simulator window with the results will open and delays can be analyzed using the zoom feature. Figure 11: "Processes" window for generating the post-route simulation results