COE328 Course Outline. Fall 2007

Size: px

Start display at page:

Download "COE328 Course Outline. Fall 2007"

Drusilla Gibbs
5 years ago
Views:

1 COE28 Course Outline Fall Objectives This course covers the basics of digital logic circuits and design. Through the basic understanding of Boolean algebra and number systems it introduces the student to the fundamentals of combinational logic design and then to sequential circuits (both synchronous and asynchronous). Memory systems are also covered. Finally, the student is introduced to Register Transfer Logic design and the structured implementation of controllers and microprogrammed computers. Technological constraints such as loading factors, noise margins, and various logic families are also introduced. Modern programmable devices (PLDs) including ROMs, PALs, PLAs, CPLDs and FPGAs, as well as appropriate computer aided design (CAD) tools are also covered. There is an introduction to VHDL. Students will be provided with an opportunity to implement the PLD-based designs (using both schematic capture and VHDL) in actual chips. By the end of the course the student will be able to design, simulate, build, and debug complex combinational and sequential digital circuits based on an abstract functional specification. The student will also understand the basic internal workings of the central processing unit of a computer and its interface with memory and input/output subsystems. The course gives students sufficient preparation for the third year microprocessor system course where small microprocessor systems are explored in depth at both hardware and software levels. 2 Course Materials Textbook: Brown, S. and Vranesic, Z. Fundamentals of Digital Logic with VHDL Design, Second Edition, McGraw-Hill, Laboratory Manual: Available through the course web page: References: (on reserve in the library) 1. Hayes, J. Introduction to Digital Logic Design, Addison Wesley, 199. (Library call number TK7868.L6H29 199). 2. Wakerly, J. Digital Design: Principles and Practices, Prentice Hall, 200. (Library call number TK W4 2000).. Dewey, A. Analysis and Design of Digital Systems with VHDL, PWS Publishing Company, (Library call number TK7868D5D ). Marking Scheme The following table summarizes the marking scheme for the course. Marking Scheme Total Lab Work: 25% Midterm: 25% Final Exam: Theory Part Lab Part To obtain a passing grade in the course, a student must obtain at least 50% in both the lab and theory portions of the course. 40% 10%

2 - 2-4 Course Outline The following table summarizes the lecture and laboratory topics and course schedule. Numbers next to topics refer to the section numbers in Brown and Vranesic or Hayes that cover the topic. Some material will be supplemented with handouts. 1 Sept 2- Sept 8 (Labor Day, Monday Sept. ) INTRODUCTION TO COE28 Scope and objectives Management INTRODUCTION TO LOGIC CIRCUITS 2.1 Variables and Functions 2.2 Inversion 2. Truth tables 2.4 Logic gates and networks 2.5 Boolean Algebra Lab 0: Orientation: Using Computers and Network & Kit purchasing details (To be done during week 2 together with Lab 1) A.5-inch floppy disk, formatted for 1.44 Mbytes is required for this introductory lab. The Lab Kit is required for week 5 2 Sept 9- Sept 15 Sept 16- Sept 22 INTRODUCTION TO LOGIC CIRCUITS 2.6 Synthesis Using AND, OR, and NOT Gates 2.7 NAND & NOR Logic Networks 2.8 Design Examples 2.9 Introduction to CAD tools 2.10 Introduction to VHDL IMPLEMENTATION TECHNOLOGY.1 Transistor switches.2,. NMOS and CMOS Logic Gates.5 Standard Chips.6 Programmable Logic Devices IMPLEMENTATION TECHNOLOGY.7 Custom Chips, Standard Cells, and Gate Arrays.8 Practical Aspects.9 Transmission Gates.10 Implementation Details for CPLDs and FPGAs OPTIMIZATION OF COMBINATIONAL LOGIC 4.1 Karnaugh Map 4.2 Strategy for Minimization (Sum-of-Products Forms) 4. Minimization of Product-of-Sums Forms 4.4 Incompletely specified functions 4.5 Multiple-Output Circuits Lab 1: Introduction to CAD Tools (2 weeks) 10 marks are given for this lab up to the end of week 4. After week 4, no marks will be assigned.

3 - - 4 Sept 2- Sept 29 OPTIMIZATION OF COMBINATIONAL LOGIC 4.6 Multilevel Synthesis 4.7 Analysis of Multilevel Circuits 4.12 Examples of Circuits Synthesized from VHDL code NUMBER REPRESENTATION AND ARITHMETIC CIRCUITS 5.1 Positional Number Representation 5.2 Addition of Unsigned Numbers 5. Signed Numbers 5.4 Fast Adders 5.5 Design of Arithmetic Circuits Using CAD 5.7 Other Number Representations 5.8 ASCII Character Code Lab 2: Function Implementation and Minimization (1 week) 10 marks are given for this lab up to the end of week 5. During week 6, 5 marks will be deducted. After week 6, no marks will be assigned. 5 Sept 0- Oct 6 6 Oct 7- Oct 7 Oct 14- Oct 20 COMBINATIONAL CIRCUIT BUILDING BLOCKS 6.1 Multiplexers 6.2 Decoders 6. Encoders 6.4 Code Converters 6.5 Arithmetic Comparison Circuits 6.6 VHDL for Combinational Circuits 7.1 Basic Latch 7.2 Gated SR-Latch 7. Gated D Latch 7.4 Master-Slave and Edge-Triggered D Flip-Flops 7.5 T Flip-Flop 7.6 JK Flip-Flop 7.7 Summary of Terminology Thanksgiving, Monday Oct Registers 7.9 Counters MIDTERM TEST Lab : Adder and Substractor Unit (2 weeks) 15 marks are given for this lab up to the end of week 6. During week 7, provided Lab 4 is completed, 5 marks will be deducted. After week 7, no marks will be assigned Lab 4: Scanning Encoder (1 week) 20 marks are given for this lab up to the end of week 7 and also week 8, provided Lab 5 is completed. During week 9, 5 marks will be deducted, again provided Lab 6 is completed. After week 9 no marks will be assigned.

4 - 4-8 Oct 21- Oct 27 Lab 5: VHDL for Combinational Circuits and Storage Elements (1 week) 7.10 Reset Synchronization 7.11 Other Types of Counters 7.12 Using Storage Elements with CAD Tools 7. Using Registers and Counters with CAD Tools SYNCHRONOUS SEQUENTIAL CIRCUITS 8.1 Basic Design Steps 8.2 State Assignment Problem 15 marks are given for this lab up to the end of week 9. During week 10, 5 marks will be deducted. After week 10, no marks will be assigned. 9 Oct 28- Nov 10 Nov 4- Nov 12 SYNCHRONOUS SEQUENTIAL CIRCUITS 8. Mealy State Model 8.4 Design of Finite State Machine Using CAD Tools 8.6 State Minimization 8.7 Design of Counter Using the Sequential Circuit Approach 8.9 Analysis of Synchronous Sequential Circuits REGISTER-LEVEL DESIGN 8.1 General Characteristics [Hayes, pp , ,6] Datapath and Control Units [Hayes, , , ] SYSTEM ARCHITECTURE 9.1 Basic System Architecture [Hayes, ] Lab 7 (Project) Discussion Lab 6: VHDL for Sequential Circuits: Implementing an Eight State Machine (1 week) All students are to start this Lab at this time. 20 marks are given for this lab up to the end of week 9 and also week 10, provided Lab 7 is completed. During weeks 11 and 12, 5 marks will be deducted, again provided Lab 7 is completed. After week 12, no marks will be assigned. Lab 7: Programmable Processor Module ( weeks) All students are to start this Lab at this time. Earlier Lab 6 as yet unfinished will be evaluated only after Lab 7 has been fully completed. Late Labs will be assigned discounted marks. 0 marks are given for this lab up to the end of week. Total Lab Marks = 120

5 Nov - SYSTEM ARCHITECTURE Nov CPU, Memory, and Input/Output [Hayes, ] 9.4 CPU Operation [Hayes, ] Faculty/Course Evaluation 12 Nov 18- Nov 24 ASYNCHRONOUS SEQUENTIAL CIRCUITS 9.1 Asynchronous Behavior 9.2, 9. Analysis and Synthesis of Asynchronous Circuits 9.6 Hazards Nov 25- Dec REVIEW AND CATCH-UP FINAL EXAMINATION Lab catch-up 5 Lab Management Labs will be graded 20 marks maximum for 1 to 2 week labs and 0 marks for the final lab to a maximum of 120 marks which will be scaled to 25% of the final mark. Credit for labs will be based on the quality of pre-lab preparation, how the Lab works (demonstration) and how well the student can answer questions about the lab. Labs where pre-lab preparation is inadequate will be marked as 0, although the student will be given an opportunity to rectify his or her preparation. Partial marks may be assigned at the discretion of the instructor. Lab 7 is to be done as a Formal Report. Refer to the lab manual on the report requirements. All of the required course specific written reports will be assessed not only on their technical or academic merit, but also on the communication skills of the author as exhibited through these reports. Each student must also keep a complete and continuous record in a binder of the year s lab activities. There are 11 stations in the lab and Labs are done in groups by 2 students or individually. Equipment should not be moved during the lab; if you believe equipment to be defective, report it to the lab instructor who will take care of the problem. Marking Scheme & Schedule for Lab Work Week Lab Week 1 #0 Self-Study Orientation (No need to go to the lab) #1 (10 marks) CAD Tools Tutorial 4 #2 (10 marks) Functional Implementation &Minimization # (15 marks) Adder and Subtractor #4 (20 marks) Scanning Encoder 7 8 SYNC #5 (15 marks) Combinational Circuits #6 (20 marks) Sequential Circuits SYNC #7 (0 marks) Programmable Processor Module 12-5: 5 mark deduction; SYNC: must start the scheduled lab.

Microprocessor Design

Microprocessor Design Principles and Practices With VHDL Enoch O. Hwang Brooks / Cole 2004 To my wife and children Windy, Jonathan and Michelle Contents 1. Designing a Microprocessor... 2 1.1 Overview