211: Computer Architecture Summer 2016

Transcription

1 211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic

2 - Digital Logic: Recap - Review: truth table => SOP => simplification - dual / complement - Minterm / Maxterm - SOP <=> POS - Combinational Circuit Rutgers University Liu Liu 2

3 - Digital Logic: Today s Topic - Review: Dual / Complement / NAND / implicants / Don t Care - Review: Decoder / Light Design / Mux - Full Adder / Overflow Rutgers University Liu Liu 3

4 Duals All boolean expressions E have duals E* if(e), we cannot tell E* if(e1 <=> E2), we can tell E1* <=> E2* To form a dual 1. replace AND with OR, OR with AND 2. replace 1 with 0, 0 with 1 Rutgers University Liu Liu 4

5 Complement All boolean expressions E have complements E if(e) then E = false if(e1 <=> E2), then E1 <=> E2 Any theorem you prove, you can also prove for the complement To form a complement 1. replace AND with OR, OR with AND 2. replace 1 with 0, 0 with 1 3. replace X to X Rutgers University Liu Liu 5

6 Relationship between Complement and Duals Rutgers University Liu Liu 6

7 Using Duals for Gate Manipulation Rutgers University Liu Liu 7

8 Converting Circuits to all-nand (NOR) Go from left to right When manipulating AND/OR gate, stick in pairs of NOT gates Isolated NOT gates can be implemented as NAND (NOR) Rutgers University Liu Liu 8

9 Canonical Forms: SOP POS We have studied two canonical forms 1. Sum of Products (SoP) 2. Product of Sums (PoS) How to convert to SoP from PoS (multiply through) How to convert to PoS from SoP (complement twice, in between multiply through) Rutgers University Liu Liu 9

10 K-maps and Implicants Rutgers University Liu Liu 10

11 Implicants Rutgers University Liu Liu 11

12 More Implicant Terminology Implicant: product term, which when viewed in a K-map, is a rectangle of 1s Prime implicant: an implicant not contained in another implicant Essential prime implicant: a prime implicant that is the only prime implicant to cover some minterm Rutgers University Liu Liu 12

13 Example Rutgers University Liu Liu 13

14 Product of Sums Example Rutgers University Liu Liu 14

15 Don t Care Conditions Rutgers University Liu Liu 15

16 Don t Cares can Greatly Simplify Circuits Rutgers University Liu Liu 16

17 Decoder Example Rutgers University Liu Liu 17

18 2:4 Decoder from 1:2 Decoders Rutgers University Liu Liu 18

19 Hierarchical 3:8 Decoder Rutgers University Liu Liu 19

20 Design Example Rutgers University Liu Liu 20

21 Design Example Rutgers University Liu Liu 21

22 Design Example We will do f, but you should be able to design a-e as well Rutgers University Liu Liu 22

23 Multiplexers (Muxes) Combinational circuit that selects binary information from many inputs to one output Rutgers University Liu Liu 23

24 Internal Mux Organization Rutgers University Liu Liu 24

25 Functions with Decoders or Muxes Rutgers University Liu Liu 25

26 Addition: The Half Adder Addition of 2 bits: A & B produces summand (S) and carry (C) But to do addition, we need 3 bits at a time (to account for carries) Rutgers University Liu Liu 26

27 The Full Adder Takes as input 2 digits (A&B) and previous carry (P) Rutgers University Liu Liu 27

28 5-bit Ripple Carry Adder Note how computation ripples from left to right Each adder has depth 2 (input passes through 2 gates to reach output) Full adder that computes s i cannot start its computation until previous full adder computes carry The longest depth in a k-bit ripple carry adder is 2k Rutgers University Liu Liu 28

29 Adder/Subtractor in 2 s Complement Form Recall A-B = A+(-B) Rutgers University Liu Liu 29

30 Handling Overflow Rutgers University Liu Liu 30

31 Overflow Computation in Adder/Subtractor For 2s complement, overflow if 2 most significant carries differ Rutgers University Liu Liu 31

32 Shifter Circuit Rutgers University Liu Liu 32

33 Barrel Shifter with Wraparound Using Muxes Rutgers University Liu Liu 33

34 Latches Set/Reset D Flip-flops Enabled Resettable Registers Now on to Sequential Circuits Rutgers University Liu Liu 34

35 How are Sequential Circuits different from Combinational Circuits? Outputs of sequential logic depend on both current and prior values it has memory Definitions: State: all the information about a circuit to explain its future behavior Latches and flip-flops: state elements that store one bit of state Synchronous sequential elements: combinational logic followed by a bank of flip-flops Rutgers University Liu Liu 35

36 Bistable Circuits Fundamental building blocks of other elements No inputs Two outputs (Q and Q ) Rutgers University Liu Liu 36

37 Consider all the cases Bistable Circuit Analysis Bistable circuit stores 1 bit of state (Q, or Q ) But there are no inputs to control state Rutgers University Liu Liu 37

38 Set/Reset Latch Rutgers University Liu Liu 38

39 S/R Latch Analysis Rutgers University Liu Liu 39

40 S/R Latch Analysis Rutgers University Liu Liu 40

41 S/R Latch Symbol Set operation makes output 1 (S = 1, R = 0, Q = 1) Reset operation makes output 0 (S = 0, R = 1, Q = 0) Remain - Keeps output as before(s = 0, R = 0, Q = Qprev) Rutgers University Liu Liu 41

42 D Latch Two inputs (C and D) C(Control): controls when the output changes D (Data input): controls what the output changes to When C = 1, D passes through to Q (transparent latch) When C = 0, Q holds previous value (opaque latch) Rutgers University Liu Liu 42

43 D Latch Internal Circuit Rutgers University Liu Liu 43

44 What are we going to do with Flip-Flops? To do computations, we need more than just combinational circuits We need to use past circuit state to influence future output But how do we coordinate computations and the changing of state values across lots of different parts of a circuit? We use CLOCKING (eg. 1GHz clock on Intel processors) On each clock pulse(high volt), combinational computations are performed, and results stored in latches How to introduce clocks into latches? Rutgers University Liu Liu 44

45 Flip-flops: Latches on a Clock A straightforward latch is not safely synchronous (or predictably synchronous) Flip-flops designed so that outputs will NOT change within a single clock pulse Rutgers University Liu Liu 45

46 D Flip-Flop Summary Rutgers University Liu Liu 46

47 Flip-Flop Activation Time Rutgers University Liu Liu 47

48 Two inputs: Clk, D Function D Flip-Flop Summary The flip-flop samples D on rising clock edge When clock goes from 0 to 1, D passes through Q Otherwise, Q holds its value Q only changes on dropping clock edge Flip-flop is called edge-triggered because it is activated only on the clock edge Rutgers University Liu Liu 48

49 Flip-Flop versus Latch Rutgers University Liu Liu 49

50 Registers Rutgers University Liu Liu 50

51 Enabled Flip-Flops Inputs: Clk, D, En The enable input (EN) controls when new data (D) is stored Function EN = 1: D passes through to Q on clock edge(set 1 register) EN = 0: the flip-flop retains its previous state(keeps others) Rutgers University Liu Liu 51

52 Inputs: Clk, D, Reset Resettable Flip-Flops Function Reset = 1: Q is forced to 0 Reset = 0: the flip-flop behaves like an ordinary D flip-flop Rutgers University Liu Liu 52

53 Resettable Flip-Flops (2) Two types Synchronous: resets at clock edge only Asynchronous: resets immediately when Reset = 1 Asynchronously resettable flip-flop requires changing the internal circuitry of the flip-flop What about synchronous design? Rutgers University Liu Liu 53

54 Synchronous Sequential Logic Design Registers contain the state of the system The state changes at the clock edge, so the system is synchronized to the clock Rutgers University Liu Liu 54

55 Shift Register Shift right Move each bit one position right Rightmost bit is dropped Assume 0 shifted into leftmost bit Register contents before shift right Register contents after shift right a Q: Do four right shifts on 1001, showing value after each shift A: 1001 (original) Implementation: Connect flipflop output to next flip-flop s input shr_in a a 28 Rutgers University Liu Liu 55

56 Shift Register To allow register to either shift or retain, use 2x1 muxes shr: 0 means retain, 1 shift shr_in: value to shift in May be 0, or 1 Why do we need shift registers? shr_in shr x1 D D D D shr_in shr Q Q Q Q Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 Rutgers University Liu Liu 56