UNIVERSITI MALAYSIA PERLIS. DMT 233 Digital Fundamental II [Asas Digit II]
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1 UNIVERSITI MALAYSIA PERLIS Peperiksaan Semester Pertama Sidang Akademik 2013/2014 Oktober 2013 DMT 233 Digital Fundamental II [Asas Digit II] Masa: 3 jam Please make sure that this question paper has FIFTEEN (15) printed pages including this front page before you start the examination. [Sila pastikan kertas soalan ini mengandungi LIMA BELAS (15) muka surat yang bercetak termasuk muka hadapan sebelum anda memulakan peperiksaan ini.] This question paper has SIX questions. Answer any FIVE questions. [Kertas soalan ini mengandungi ENAM soalan. Jawab mana-mana LIMA soalan.] Please answer questions 1(b), 1(d), 4(b)(i) and 4(c) in Appendix I, II, III and IV respectively. [Sila jawab soalan-soalan 1(b), 1(d), 4(b)(i) dan 4(c) masing-masing dalam Lampiran I, II, III dan IV.]
2 - 2 - Question 1 [Soalan 1] (a) Flip-flops and latches are fundamental building blocks of digital electronic systems used in computers, communications, and other types of system. [Flip-flop dan selak adalah satu blok binaan utama sistem digital elektronik yang digunakan dalam komputer, komunikasi, dan banyak jenis-jenis system yang lain.] (i) Define combinational circuit. [Takrifkan litar gabungan.] (ii) Sketch the sequential circuit. [Lakarkan litar jujukan.] (b) Figure 1(a) shows a combination of SR flip-flop and logic gates. A, B and C are the data input signals while Q is the output. Complete the truth table of this circuit in Appendix I. [Rajah 1(a) menunjukkan suatu kombinasi flip-flop SR dan get-get logik. A, B dan C adalah isyaratisyarat masukan data manakala Q adalah keluaran. Lengkapkan jadual kebenaran bagi litar ini dalam Lampiran I.] Figure 1(a) [Rajah 1(a)]. 3/-
3 - 3 - (c) With aid of a diagram, briefly explain the application of flip-flops as Frequency Division. [Dengan bantuan gambarajah, terangkan secara ringkas aplikasi flip-flop sebagai Pembahagi Frekuensi.] (d) Figure 1(b) shows a combination of flip-flops and latch. Draw the output waveform of signals W, X, Y and Z in Appendix II. Assume that all the output values are initially at 0. [Rajah 1(b) menunjukkan suatu kombinasi flip-flop dan selak. Lukiskan gelombang keluaran bagi isyarat-isyarat W, X, Y dan Z dalam Lampiran II. Andaikan bahawa semua nilai keluaran adalah bermula pada 0.] (8 Marks / Markah) Figure 1(b) [Rajah 1(b)]
4 - 4 - Question 2 [Soalan 2] Counter is a digital circuit which is able to count from a specific number to another specific number according to the requirement. [Pembilang ialah satu litar berdigit yang mana mampu mengira dari satu angka tepat kepada satu lagi angka tepat menurut keperluan.] (a) Sketch the synchronous and asynchronous counter. [Lakarkan pembilang segerak dan tak segerak.] (b) Compare synchronous and asynchronous counter. [Bandingkan pembilang segerak dan tak segerak.] (c) List TWO(2) the application of a counter in our daily life. [Senaraikan DUA(2) aplikasi bagi sebuah pembilang dalam kehidupan seharian kita.] (d) Construct a modulus-13 asynchronous counter with a straight binary sequence from 0000 through 1011 using JK flip-flop. [Binakan suatu pembilang tak segerak modulus-13 dengan suatu jujukan perduaan lurus dari 0000 hingga 1011 menggunakan flip-flop JK.]. 5/-
5 - 5 - (e) Figure 2(a) shows a configuration of a cascaded counter. Determine; [Rajah 2(a) menunjukkan konfigurasi bagi sebuah pembilang lata. Tentukan;] MHz DIV 6 DIV 2 DIV 8 DIV 4 DIV 12 Figure 2(a) [Rajah 2(a)] (i) frequency of the waveform at each point indicated by circled number. [frekuensi untuk gelombang bagi setiap titik yang ditunjukkan oleh nombor yang dibulatkan.] (ii) overall modulus. [modulus keseluruhan.] (f) Determine the counter sequence in Figure 2(b). Assume that Q 2, Q 1 and Q 0 are initially at 0. [Tentukan jujukan pembilang dalam Rajah 2(b). Andaikan bahawa Q 2, Q 1 dan Q 0 bermula pada 0.] (6 Marks / Markah) Figure 2(b) [Rajah 2 (b)]
6 Question 3 [Soalan 3] Figure 3 shows a synchronous counter sequence of a system. Assume that variable S is a control signal. [Rajah 3 menunjukkan suatu jujukan pembilang segerak bagi suatu sistem. Andaikan bahawa pembolehubah S adalah sebuah isyarat kawalan.] Figure 3 [Rajah 3] (a) Construct a transition table for SR flip-flop. [Binakan sebuah jadual perubahan untuk flip-flop SR.] (b) Construct the state table. [Binakan jadual keadaan.] (c) Develop Karnaugh maps for each input of SR flip-flops. [Bangunkan peta-peta Karnaugh untuk setiap masukan flip-flop SR.] (d) Derive the simplified Boolean expressions. [Terbitkan ungkapan-ungkapan Boolean yang termudah.] (e) Draw the counter circuit for 3(d). [Lukiskan litar pembilang bagi 3(d).] (6 Marks / Markah) (3 Marks / Markah) (5 Marks / Markah)
7 Question 4 [Soalan 4] Shift Registers are a type of sequential logic circuit closely related to digital counters and primarily used for data storage. [Daftar Anjak ialah sejenis litar mantik jujukan berkait rapat dengan pembilang-pembilang digital dan terutamanya digunakan untuk storan data.] (a) List FOUR (4) types of Shift Register. [Nyatakan EMPAT (4) jenis Daftar Anjak.] (b) Figure 4(a) shows a Shift Register operation. [Rajah 4(a) menunjukkan operasi suatu Daftar Anjak.] (i) (ii) Explain the movements of data bits through this Shift Register. [Terangkan pergerakan-pergerakan bagi bit-bit data melalui Daftar Anjak ini.] Complete the timing diagram in Appendix III for the shift register in Figure 4(a) by assuming the register is initially cleared. [Lengkapkan gambarajah pemasa dalam Lampiran III bagi daftar anjak dalam Rajah 4(a) dengan menganggapkan pendaftar tersebut dikosongkan pada mulanya.] (8 Marks / Markah) Figure 4(a) [Rajah 4(a)]. 8/-
8 - 8 - (c) The group of bits 1010 is serially shifted (right-most bit first) into a 4-bit parallel output shift register in Figure 4(b). Determine the data bits stored after three clock pulses in Appendix IV by assuming that the shift register is initially [Sekumpulan bit-bit 1010 dianjak secara sesiri (bit pertama paling-kanan) ke dalam 4-bit keluaran selari daftar anjak dalam Rajah 4(b). Tentukan bit-bit data yang disimpan selepas tiga jam dedenyut dalam Lampiran IV dengan mengandaikan permulaan daftar anjak adalah 1001 pada permulaan.] Figure 4(b) [Rajah 4(b)] (d) Johnson counter and ring counter are two types of shift register counter. [Pembilang Johnson dan pembilang cincin adalah dua jenis pembilang daftar anjak.] (i) (ii) Differentiate Johnson counter and ring counter. [Bezakan pembilang Johnson dan pembilang cincin.] Sketch a 2-bit Johnson counter. [Lakarkan sebuah pembilang Johnson 2-bit.]
9 Question 5 [Soalan 5] (a) Explain the representations in a state diagram below; [Takrifkan terma-terma berikut:] (i) (ii) (iii) circles. [bulatan-bulatan.] arcs. [anak panah- anak panah.] labels. [label-label.] (1 Mark / Markah) (1 Mark / Markah) (1 Mark / Markah) (b) Sketch and differentiate Moore and Mealy Model. [Lakar dan bezakan Model Moore dan Mealy.]. 10/
10 (c) Refer to Figure 5, X is an input; Y1 and Y0 are the outputs. Assume initial state is S0. [Rujuk pada Rajah 5, X adalah satu masukan, Y1 dan Y0 adalah keluaran-keluaran. Andaikan keadaan awalan ialah S0.] Figure 5 [Rajah 5] (i) Produce the corresponding state table using D flip-flop. [Hasilkan jadual keadaan sepadan menggunakan flip-flop D.] (6 Marks / Markah) (ii) (iii) Derive the simplified Boolean expressions. [Terbitkan ungkapan-ungkapan Boolean termudah.] Design an equivalent logic circuit. [Rekabentuk sebuah litar logik yang setara.] (3 Marks / Markah)
11 Question 6 [Soalan 6] (a) Briefly explain the design procedure in sequential circuit design. [Terangkan secara ringkas prosedur rekabentuk dalam rekabentuk litar jujukan.] (b) Figure 6 shows a sequential circuit system of two T flip-flops, A and B. [Rajah 6 menunjukkan suatu sistem litar jujukan bagi dua flip-flop T, A dan B.] Figure 6 [Rajah 6] (i) State the Boolean expressions for both T flip-flop input and the output, Z. [Nyatakan ungkapan-ungkapan Boolean bagi kedua-dua masukan T flip-flop dan keluaran, Z.] (3 Marks / Markah) (ii) (iii) Construct the state table. [Bina jadual keadaan.] Draw the state diagram for 6(b)(ii). [Lakar gambarajah keadaan bagi 6(b)(ii).] (8 Marks / Markah) (iv) Identify the state diagram model in Figure 6. [Kenalpasti model gambarajah keadaan dalam Rajah 6.] (1 Mark / Markah) -ooo-
12 Appendix I [Lampiran I] Question 1(b) [Soalan 1(b)] Index Number: Table No. [Angka Giliran]: [No. Meja]: Input Flip-flop Input Output A B C S R Q Q
13 Appendix II [Lampiran II] Question 1(d) [Soalan 1(d)] Index Number: Table No. [Angka Giliran]: [No. Meja]: CLK A B W X Y Z
14 Appendix III [Lampiran III] Question 4(b)(ii) [Soalan 4(b)(ii)] Index Number: Table No. [Angka Giliran]: [No. Meja]: CLK Data input Q0 Q1 Q2 Q3
15 Appendix IV [Lampiran IV] Question 4(c) [Soalan 4(c)] Index Number: Table No. [Angka Giliran]: [No. Meja]: CLK Data input
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