SG4424 HDTV Slave Sync Generator User Guide

Transcription

1 SG4424 HDTV Slave Sync Generator User Guide INTRODUCTION The SG4424LP HDTV Slave Sync Generator locks to either an NTSC or PAL reference signal and generates HD tri-level sync per SMPTE 274M (1080i/p) and SMPTE 296M (720p). The HD format is selected by an internal DIP switch. In addition, the generator provides three timing signals to assist in post production. These include SD525i/60, SD625i/48, and Field 1 Line 1 vertical alignment pulse which indicates when the 525i/60 and 625i/48 F1L1 s match (every 167 ms). The Divisor switch drops all output field rates by 0.1% (1/1.001). Key features of the module include the following: Multi-format HD tri-level sync generation Supports the following formats: 1080i/ sF/ p/ i/ sF/ p/ i/ sF/ p/ i/ sF/ p/ i/ sF/ p/ i/ sF/ p/ p/60 720p/59.94 (i stands for interlaced, p for progressive, and sf for segmented frame.) Frame rate divisor (M = 1 or 1/1.001) controls all output rates Locks to NTSC or PAL reference input Provides three additional timing signals: SD525i/60 sync SD625i/48 sync Field 1 Line 1 alignment signal LED indicators for NTSC and PAL reference inputs and output signal Lock The SG4424LP HDTV Slave Sync Generator consists of a Processing Card and an I/O Card. The Processing Card installs at the front of the 4000 Series Frame and connects to the motherboard, occupying one slot in the frame. This card exchanges signal data with the I/O Card and the Control Card through the motherboard. In addition, the Processing Card receives ± 15 VDC from the Power Supply through the motherboard and produces regulated ±12, +5 and +3.3 VDC power for on-board circuits and for the I/O Card. Page

2 The I/O Card provides the interface between external devices and the Processing Card. It installs in back of the 4000 frame and connects to the motherboard in the slot directly behind the associated Processing Card. Processing Card Panel Description Figure 1 illustrates the SG4424LP HDTV Slave Sync Generator front panel. Front panel LEDs, visible when the 4000 Series frame door is open, are described below. Ref Input Power NTSC PAL Divisor 1 1 SG4424LP HDTV Sync Generator Lock Out 1-2: HD Tri Level Sync Out 3: SD Analog Sync 625i / 48 Out 4: SD Analog Sync 525i / 60 Out 6: Field 1 Line 1 Align Pulse NVIsi on Power NTSC & PAL Ref Inputs Divisor Switch Lock Figure 1. SG4424LP HDTV Slave Sync Generator Panel Power - This green LED is normally On to indicate that the module is receiving power from the NV4001/2 frame power supply through the motherboard. An on-board power supply then produces the +12, -12, +3.3 and +5VDC required by the module. Ref Input - The green NTSC or PAL LED is normally On to indicate that the module is receiving the reference input signal. Divisor Switch - If enabled by DIP switch S6-4, divides all output signals by 1 or The 1 divisor produces outputs of 60, 50, and 48 fields per second and 30, 25, and 24 progressive frames per second. The divisor produces outputs of 59.94, and fields per second and 29.97, , and progressive frames per second. Lock - This green LED indicates the output signal is locked to the reference input. See Clock Lock on page 9 for details. Page

3 I/O Card Panel Description The I/O Card consists of a BNC connector and a loop-thru BNC connector for each of the NTSC and PAL Reference inputs and 5 outputs. Figure illustrates the I/O Card rear panel. Note that Output 5 is unused. Loop Loop Out 1 Out 2 Out 3 Out 4 Out 5 Out 6 SYNC GEN REF NTSC REF PAL SG4424 NTSC Ref In PAL Ref In HD Sync Out SD Analog Sync Out 625i/48 SD Analog Sync Out 525i/60 Field 1 Line 1 Align Pulse Out Figure 2. SG4424LP HDTV Slave Sync Generator Panel NTSC Ref In - Accepts a standard NTSC analog video input. Loop-thru connector and on-board jumper termination are provided. PAL Ref In - Accepts a standard PAL analog video input. Loop-thru connector and onboard jumper termination are provided. HD Sync Out - A tri-level high definition sync output that can be set via on-board DIP switch for the following standards: - 274M 1080 lines interlaced format at 60, 50, and 48 fields/second - 274M 1080 lines progressive format at 30, 25, and 24 frames/second - 296M 720 lines progressive format at 60 frames/second SD Analog Sync Out 625i/48-625i/50 sync output time-stretched to 625i/48 (divisor 1) or 625i/ (divisor 1.001) SD Analog Sync Out 525i/60-525i/59.94 sync output (divisor 1.001) or time-compressed to 525i/60 (divisor 1) Field 1 Line 1 Out - Indicates when Field 1 Line 1 of the SD625 and SD525 outputs are aligned (every 6 Hz or 167 ms). Page

4 SPECIFICATIONS Table 1. SG4424LP HDTV Slave Sync Generator Specifications Type Parameter General Power Power Consumption Size Input Power: ±15VDC input from 4000 Series frame On-Board Power: ±12, +5, and +3.3 VDC 6.5 watts Processing Card: (14.3mm) H x (155.6mm) W x (314.3mm) D. I/O Card: (14.3mm) H x (155.6mm) W x (76.6mm) D. Weight 1.25 lbs (0.6kg) max. Inputs 1 Composite NTSC 525i/ analog video, BNC loop-thru 1 Composite PAL 625i/50 analog video, BNC loop-thru Input Impedance: 75Ω or Hi-Z Input signal Level: 1 Vpp nominal Input Impedance: 75Ω or Hi-Z Input signal Level: 1 Vpp nominal Outputs Out 1 & 2, SMPTE 274M Analog HD Tri-level Sync: 1080i/60, 1080i/ i/50, 1080i/ i/48, 1080i/ p/30, 1080p/ p/25, 1080p/ p/24, 1080p/ p/60, 720p/59.94 Out 3, SD Analog Sync: 625i/48, 625i/ Out 4, SD Analog Sync: 525i/60, 525i/59.94 Out 6, Field 1 Line 1 Align Pulse Output Impedance: 75Ω Output Signal Level: ±300 mv nominal Output Impedance: 75Ω Sync Tip Level: -300 mv Output Impedance: 75Ω Sync Tip Level: -286 mv Output Impedance: 75Ω Sync Tip Level: -286 mv Sync Pulse Width: 114 µs Page

5 CONFIGURATION Use the information here to configure your SG4424LP HDTV Slave Sync Generator. Configuring the 4424 requires setting jumpers J1 and J2 for input impedance, setting DIP switch S6 for output signal format, and setting the Divisor switch. Figure 3 highlights the jumper and DIP switch locations, and the following tables list possible settings. S6 Figure 3. SG4424LP HDTV Slave Sync Generator Card Jumpers and Switches Page

6 Table 2. Jumper and DIP Switch Settings Component Function Settings Jumper J1 PAL input termination Select 75Ω or Hi-Z Jumper J2 NTSC input termination Select 75Ω or Hi-Z Table 3. Settings for DIP Switch S6, Switches 1-5 Component Function Settings DIP Switch S6-1 Broad Pulse Width for Output 1 when in 1080i/48 HD mode (see Output Signals on page 8) On = Extended Broad Pulse (ηi = 1287) Off = SMPTE (ηi = 1012) DIP Switch S6-2 Select Input Reference On = PAL Off = NTSC DIP Switch S6-3 Operational Mode On = Slave Sync Gen Off = Test Mode (free run) DIP Switch S6-4 Divisor Switch Select On = Use Internal Divisor Switch (S6-5) Off = Use External Divisor Switch (front) DIP Switch S6-5 Internal Divisor Switch Off = Divisor is 1 On = Divisor is 1/1.001 Table 4. Settings for DIP Switch S6, Switches 6-8 Component Function Format S6-6 S6-7 S6-8 DIP Switch S6 6-8 HD Sync Format 1080i/60 On Off On 1080i/50 Off On On 1080i/48 On On On 1080p/30 On On Off 1080p/25 Off On Off 1080p/24 On Off Off 720p/60 Off Off Off Page

7 INSTALLATION The module can be installed (by qualified personnel only) with frame power on. Installation entails inserting the processing module into an available front slot of the 4000 frame and inserting the I/O module in the rear slot directly behind the processing module. THEORY OF OPERATION The SG4424LP HDTV Slave Sync Generator accepts NTSC and PAL video inputs and produces the following four outputs that are clock-locked to the selected input: SMPTE 274M/296M HD tri-level sync, SD625 sync, SD525 sync, and Field 1 Line 1 pulse. Please refer to Figure as you read this portion of the manual. NTSC Buffer & Sync Stripper Mux & Logic Input PLL Clock Gen & Logic Output PLL #1 Clock Gen & Logic HD Sync Generation 625 Sync Generation 2 Video Drivers Video Driver PAL Buffer & Sync Stripper Output PLL #2 Clock Gen & Logic 525 Sync Generation F1L1 Generation Video Driver Video Driver Config Switches Figure 4. SG4424LP HDTV Slave Sync Generator Block Diagram Input Circuit The SG4424LP incorporates two video input circuits and sync strippers. Input 1 accepts an NTSC signal and input 2 accepts a PAL signal. Each input has two BNC connectors to provide signal loopthru. On-board jumpers for each input allow selection of termination or loop-thru. Each sync stripper recovers H and V syncs and Field ID from the input signal. Individual validation circuits ensure that the reference input is correct and then drive the front panel NTSC and PAL presence LEDs accordingly. A DIP switch setting provides selection of either NTSC or PAL sync to drive the Input PLL circuit. Input PLL The Input PLL locks to the H sync recovered from the selected input reference. If the selected input is not validated, the input PLL is disabled along with all outputs. In test mode, the Input PLL is clamped and free runs. Page

8 Output PLLs Two Output PLLs are clock locked to the Input PLL. One Output PLL drives the HD signal generator and the SD625 signal generator. The second Output PLL drives the SD525 signal generator. The PLL output frequencies shift down by 0.1% when the Divisor switch is in the 1/1.001 position. From power-up or with an input reference connection, the module takes about ten (10) seconds to achieve lock. FPGA Clock Generator & Logic The Clock Generator and Logic FPGA (Field Programmable Gate Array) accepts the reference input signals and provides the logic and clock outputs that control the PLLs. The FPGA includes phase detectors that ensure phase lock and divides the phase-locked signals to produce the various output sync signals in digital form. Output Signals The SG4424LP provides four types of sync output signals: HD Tri-level; SD 625; SD 525; and F1L1 Align. All outputs are disabled while the PLLs are not locked. HD Tri-level Sync, Outputs 1 and 2: The HD tri-level sync is available on Outputs 1 and 2. It is DIP switch configurable so that with the Divisor switch set to 1, it provides either SMPTE 274M 1080 line reference for interlaced (and Segmented Frame) format at 60, 50, and 48 fields per second, or progressive format at 30, 25, and 24 frames per second, or SMPTE 296M 720 line reference progressive format at 60 frames per second. Broad pulse width at Output 1 may be set for Extended or SMPTE standard when 1080i/48 HD mode is selected. With the Divisor switch set to 1/1.001, the rates change. The 1080 line reference at 60, 50, and 48 fields per second change to 59.94, 49.95, and fields per second respectively; the progressive format at 30, 25, and 24 frames per second change to 29.97, , and frames per second respectively; and the 720 line reference progressive format at 60 frames per second changes to frames per second. SD Analog Sync 625i/48,Output 3: The SD625/48 sync appears at Output 3. This output consists of V and H sync pulses only (no color burst, video, etc). With the Divisor switch set to 1/1.001, the rate changes to fields per second. SD Analog Sync 525i/60,Output 4: The SD525/60 sync appears at Output 4. This output consists of V and H sync pulses only (i.e., no color burst, video, etc). With the Divisor switch set to 1/1.001, the rate of the output changes to fields per second. Output 5: Not used. Field 1 Line 1 Align Pulse, Output 6: The F1L1 (Field 1 Line 1) Align signal indicates when F1L1 of the SD625 output and F1L1 of the SD525 output are aligned. (This occurs every 6Hz or 167ms.) The output level matches the SD525 output with the alignment indicated by an H pulse. Page

9 Clock Lock During normal operation, all outputs are clock locked to the selected input reference. When the Input PLL and both Output PLLs are locked to the input reference, the front panel Lock LED turns On. In Test Mode (described later), the Input PLL free-runs and does not attempt to lock to the input reference. When the Output PLLs lock to the Input PLL, the front panel Lock LED flashes. Genlock Due to non-matching line and field rates, it is not possible for most outputs to Genlock to the input references. However, the SD525 output Genlocks to the NTSC input when the Divisor switch is set to 1/ Note that there is no phase adjustment capability. Frame Lock Under specific conditions, frame lock of the HD sync output to the input reference occurs when the frame rate of the HD sync output matches the frame rate of the selected input reference. These conditions are listed below: Input Divisor HD Mode NTSC 1/ i/59.94 NTSC 1/ p/29.97 NTSC 1/ p/59.94 PAL i/50 PAL p/25 Output Frame Alignment Output frame alignment occurs on outputs which have matching frame rates (independent of frame lock to the input reference). In addition, the SD 525 and SD 625 outputs have a Field 1 Line 1 relationship whereby they are F1L1 aligned every 6 Hz (167 ms). The F1L1 Align signal (at output 6) indicates this F1L1 coincidence between the SD outputs by generating an H sync output pulse. Specific conditions that provide output frame alignment are listed below: Divisor HD Mode Output F1L1 Aligned to HD i/60 SD 525i/60 1/ i/59.94 SD 525i p/30 SD 525i/60 1/ p/29.97 SD 525i/ p/60 SD 525i/60 Page

10 Divisor HD Mode Output F1L1 Aligned to HD 1/ p/59.94 SD 525i/ i/48 SD 626i/48 1/ i/ SD 626i/ p/24 SD 625i/48 1/ p/ SD 625i/ Test Mode The on-board DIP switch can be configured to put the Sync Generator into a free-run test mode (see Configuration). Input references are ignored and the Input PLL free-runs. The Output PLLs lock to the free-running Input PLL. All outputs are active with standard field/frame relationships. Output 2 Broad Pulse Timing for 1080i/48 HD The on-board DIP switch can be configured to allow changing the tri-level broad pulse width for the 1080i/48 (1080sF/24) format (see Configuration). It can be set per the 1998 proposed revision of SMPTE 274M (ηi = 1012) or to an Extended setting which some early 24 sf HD equipment requires (ηi = 1287). All other HD formats are unaffected by this DIP switch setting. Page

11 TROUBLESHOOTING & MAINTENANCE The module requires no routine maintenance. If it does not appear to operate correctly, first reseat the module in the frame to ensure good internal connections and then check that the Power indicator on the front of the module is lit. If the signal exhibits problems, check signal sources, cables, terminations, and switch/jumper settings, if any. For technical assistance, call or send to Table 5. Troubleshooting Checklist Symptom Module not functioning at all. Weak, distorted, or missing output signal. All outputs missing. Output does not lock reliably to input (LOCK LED is not on) Output is wrong frequency or wrong number of lines. Possible Causes and Solutions Check front panel power LED. It is on when power is applied. If it is off, check that the card connectors are contacting the motherboard connectors. Swap the Slave Sync Gen with a known good board. Check the external sources. Check all cables and connections. Check for proper termination. Swap with a known good board. The PLL circuit shuts down all outputs when the output PLLs are not locked. Check the reference inputs. The Ref LEDs on the front panel indicate whether the reference is present. Also check all DIP switch settings, especially that DIP switch S6-2 is set for the correct input reference signal (NTSC or PAL).. Check quality of input signal. Check that DIP switch S6-2 is set for the correct input reference signal (NTSC or PAL). Check the settings of DIP switch S6 and the front panel Divisor switch as explained under Configuration on page 14. Trademarks and Disclaimer NVISION is a registered trademark of NVISION, Inc. Contents herein are current as of the date of publication. NVISION reserves the right to change the contents without prior notice. In no event shall NVISION be liable for any damages resulting from loss of data, loss of use, or loss of profits and NVISION further disclaims any and all liability for indirect, incidental, special, consequential or other similar damages. This disclaimer of liability applies to all products, publications and services during and after the warranty period. Page