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1 Is Now Part of To learn more about ON Semiconductor, please visit our website at ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor omponents Industries, LL dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of ON Semiconductor s product/patent coverage may be accessed at ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. uyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. Typical parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FD lass medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should uyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, uyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

2 7UPT97 TinyLogic Low Power onfigurable Gate with oltage-level Translator Features Single Supply oltage Translator -.8 to. Input at =. -.8 to. Input at =.. to. Supply oltage Operation. Over-oltage Tolerant I/O s at from. to. Power-Off High-Impedance Inputs and Outputs Low Static Power onsumption - I =0.9µ Maximum Low Dynamic Power onsumption - PD=.7pF Typical at. Ultra-Small MicroPak Packages Ordering Information Description October 00 The 7UPT97 is a universal configurable -input logic gate that provides single supply voltage level translation. This device is designed for applications with inputs switching levels that accept.8 low voltage MOS signals while operating from either a single. or. supply voltage. The 7UPT97 is an ideal low power solution for mixed voltage signal applications especially for battery-powered portable applications. This product guarantees very low static and dynamic power consumption across entire voltage range. ll inputs are implemented with hysteresis to allow for slower transition input signals and better switching noise immunity. The 7UPT97 provides for multiple functions as determined by various configurations of the three inputs. The potential logic functions provided are MUX, ND, NND, OR, and NOR, inverter and buffer. Refer to Figures to 9. Part Number Top Mark Package Packing Method 7UPT97LX H -Lead MicroPak,.0mm Wide 7UPT97FHX H -Lead, MicroPak, xmm ody,.mm Pitch 000 Units on Tape & Reel 000 Units on Tape & Reel 7UPT97 TinyLogic Low Power onfigurable Gate with oltage-level Translation 008 Fairchild Semiconductor orporation 7UPT97 Rev..0.

3 Logic Diagram Pin onfigurations Pin Definitions Figure. Logic Diagram (Positive Logic) Figure. MicroPak (Top Through iew) Pin # Name Description Data Input Ground Data Input Output Supply oltage Data Input 7UPT97 TinyLogic Low Power onfigurable Gate with oltage-level Translator 008 Fairchild Semiconductor orporation 7UPT97.0.

4 Function Table Inputs 7UPIT97 =Output L L L L L L H L L H L H L H H H H L L L H L H H H H L L H H H H H = HIGH Logic Level L = LOW Logic Level Function Selection Table Logic Function onnection onfiguration -to- MUX Figure -Input ND Gate Figure -Input OR Gate with One Inverted Input Figure -Input NND Gate with One Inverted Input Figure -Input ND Gate with One Inverted Input Figure -Input NOR Gate with One Inverted Input Figure -Input OR Gate Figure 7 Inverter Figure 8 uffer Figure 9 7UPT97 TinyLogic Low Power onfigurable Gate with oltage-level Translator 008 Fairchild Semiconductor orporation 7UPT97.0.

5 7UPT97 Logic onfigurations Figure through Figure 9 show the logical functions that can be implemented using the 7UPT97. The diagrams show the DeMorgan s equivalent logic duals for a given two-input function. The logical Note:. When is L, =.. When is H, =. implementation is next to the board-level physical implementation of how the pins of the function should be connected. Figure. -to- MUX Figure. -Input ND Gate Figure. Input OR Gate with One Inverted Input -Input NND Gate with One Inverted Input Figure. -Input ND Gate with One Inverted Input -Input NOR Gate with One Inverted Input 7UPT97 TinyLogic Low Power onfigurable Gate with oltage-level Translator Figure 7. -Input OR Gate Figure 8. Inverter Figure 9. uffer 008 Fairchild Semiconductor orporation 7UPT97.0.

6 bsolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit Supply oltage -0.. IN D Input oltage -0.. OUT D Output oltage HIGH or LOW State () =0-0.. I IK D Input Diode urrent IN < 0-0 m I OK D Output Diode urrent OUT < 0-0 OUT > +0 I OH / I OL D Output Source / Sink urrent ±0 m I O ontinuous Output urrent ±0 m I or I D or Ground urrent per Supply Pin ±0 m T STG Storage Temperature Range - +0 T J Junction Temperature Under ias +0 T L Junction Lead Temperature, Soldering 0s +0 P D ESD Power Dissipation at +8 MicroPak- 0 MicroPak- 0 Human ody Model, JEDE:JESD harged Device Model, JEDE:JESD Note:. I O absolute maximum rating must be observed. Recommended Operating onditions () The Recommended Operating onditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to bsolute Maximum Ratings. Symbol Parameter onditions Min. Max. Unit Supply oltage.. IN Input oltage 0. OUT I OH/I OL Output oltage Output urrent =0 0. HIGH or LOW State 0 =.0 to. ±.0 =. to.7 ±. T Operating Temperature, Free ir θ J Thermal Resistance MicroPak- 00 MicroPak- 0 Note:. Unused inputs must be held HIGH or LOW. They may not float. m mw m /W 7UPT97 TinyLogic Low Power onfigurable Gate with oltage-level Translator 008 Fairchild Semiconductor orporation 7UPT97.0.

7 D Electrical haracteristics Symbol Parameter onditions P N H OH OL I IN I OFF ΔI OFF I ΔI Positive Threshold oltage Negative Threshold oltage Hysteresis oltage HIGH Level Output oltage LOW Level Output oltage Input Leakage urrent Power Off Leakage urrent dditional Power Off Leakage urrent Quiescent Supply urrent Increase in I per Input T =+ T =-0 to +8 Min. Max. Min. Max.. to to to to to to I OH=-0µ I OH=-.m.0.97 I OH=-.m.90.8 I OH=-.7m.7.7 I OH=-m.0... I OL=0µ I OL=.m I OL=.m I OL=.7m I OL=.0m Units 0 to. 0 IN. ±0.0 ±0.0 µ 0 0 ( IN, O) µ 0 to 0.. to.. to.7.0 to. IN or O=0 to µ IN= or IN. ±0.90 One Input at 0. or., other Inputs at 0 or One Input at 0. or., other Inputs at 0 or µ µ 7UPT97 TinyLogic Low Power onfigurable Gate with oltage-level Translator 008 Fairchild Semiconductor orporation 7UPT97.0.

8 Electrical haracteristics Symbol Parameter onditions t PHL, t PLH IN OUT PD Propagation Delay Input apacitance Output apacitance Power Dissipation apacitance.0.70, IN=. to , IN=.0 to , IN=.0 to , IN=. to , IN=.0 to , IN=.00 to , IN=. to , IN=.0 to , IN=.0 to , IN=. to , IN=.0 to , IN=.00 to , IN=. to , IN=.0 to , IN=.0 to , IN=. to , IN=.0 to , IN=.00 to , IN=. to , IN=.0 to , IN=.0 to , IN=. to , IN=.0 to , IN=.00 to.0 L=pF, R L=MΩ L=0pF, R L=MΩ L=pF, R L=MΩ L=0pF, R L=MΩ T =+ T =-0 to +8 Min. Typ. Max. Typ. Max Units 0. pf 0.0 pf ns pf Figure Figure 0 Figure 7UPT97 TinyLogic Low Power onfigurable Gate with oltage-level Translator 008 Fairchild Semiconductor orporation 7UPT

9 Loadings and Waveforms Symbol Figure 0. Test ircuit Figure. Waveforms. ± 0.. ± 0. mi IN/ IN/ mo / / 7UPT97 TinyLogic Low Power onfigurable Gate with oltage-level Translator 008 Fairchild Semiconductor orporation 7UPT

10 Physical Dimensions X 0.0 PIN IDENTIFIER 0.0 DETIL (0.0) X 0.MX. (0.) TOP IEW.0 0. OTTOM IEW X Notes:. ONFORMS TO JEDE STNDRD M0- RITION UD. DIMENSIONS RE IN MILLIMETERS. DRWING ONFORMS TO SME.M-99. FILENME ND REISION: M0RE. PIN ONE IDENTIFIER IS X LENGTH OF N OTHER LINE IN THE MRK ODE LOUT. Figure. -Lead, MicroPak,.0mm Wide X (0.9) X (0.) X PIN X X (0.) X 0.07 X HMFER () (0.0) X REOMMENED LND PTTERN X (0.7) DETIL PIN TERMINL Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. 7UPT97 TinyLogic Low Power onfigurable Gate with oltage-level Translator lways visit Fairchild Semiconductor s online packaging area for the most recent package drawings: Tape and Reel Specifications Please visit Fairchild Semiconductor s online packaging area for the most recent tape and reel specifications: Package Designator Tape Section avity Number avity Status over Type Status LX Leader (Start End) (Typical) Empty Sealed arrier 000 Filled Sealed Trailer (Hub End) 7 (Typical) Empty Sealed 008 Fairchild Semiconductor orporation 7UPT

11 Physical Dimensions X X PIN MIN 0uM (0.08) X DETIL TOP IEW SIDE IEW 0.MX (0.08) X OTTOM IEW NOTES:. OMPLIES TO JEDE MO- STNDRD. DIMENSIONS RE IN MILLIMETERS.. DIMENSIONS ND TOLERNES PER SME.M, 99 D. LNDPTTERN REOMMENDTION IS SED ON FS DESIGN. E. DRWING FILENME ND REISION: MGF0RE Figure. X X X 0.0 X 0. X 0. X X HMFER (0.0) X X X 0. REOMMENDED LND PTTERN FOR SPE ONSTRINED P LTERNTIE LND PTTERN FOR UNIERSL PPLITION DETIL PIN LED SLE: X -Lead, MicroPak, xmm ody,.mm Pitch Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. 7UPT97 TinyLogic Low Power onfigurable Gate with oltage-level Translator lways visit Fairchild Semiconductor s online packaging area for the most recent package drawings: Tape and Reel Specifications Please visit Fairchild Semiconductor s online packaging area for the most recent tape and reel specifications: Package Designator Tape Section avity Number avity Status over Type Status FHX Leader (Start End) (Typical) Empty Sealed arrier 000 Filled Sealed Trailer (Hub End) 7 (Typical) Empty Sealed 008 Fairchild Semiconductor orporation 7UPT

12 008 Fairchild Semiconductor orporation 7UPT UPT97 TinyLogic Low Power onfigurable Gate with oltage-level Translator

13 ON Semiconductor and are trademarks of Semiconductor omponents Industries, LL dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of ON Semiconductor s product/patent coverage may be accessed at Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. uyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. Typical parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FD lass medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should uyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, uyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PULITION ORDERING INFORMTION LITERTURE FULFILLMENT: Literature Distribution enter for ON Semiconductor 9 E. nd Pkwy, urora, olorado 800 US Phone: or Toll Free US/anada Fax: or Toll Free US/anada orderlit@onsemi.com Semiconductor omponents Industries, LL N. merican Technical Support: Toll Free US/anada Europe, Middle East and frica Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative

14 Mouser Electronics uthorized Distributor lick to iew Pricing, Inventory, Delivery & Lifecycle Information: Fairchild Semiconductor: 7UPT97FHX 7UPT97LX