Chapter 5 Sequential Circuits

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1 Logic and Computer Design Fundamentals Chapter 5 Sequential Circuits Part 2 Sequential Circuit Design Charles Kime & Thomas Kaminski 28 Pearson Education, Inc. (Hyperlinks are active in View Show mode)

2 Overview Part - Storage Elements and Sequential Circuit Analysis Part 2- Sequential Circuit Design Specification Formulation State Assignment Flip-Flop Input and Output Equation Determination Verification Chapter 5 - Part 2 2

3 The Design Procedure Specification Formulation - Obtain a state diagram or state table State Assignment - Assign binary codes to the states Flip-Flop Input Equation Determination - Select flip-flop types and derive flip-flop equations from next state entries in the table Output Equation Determination - Derive output equations from output entries in the table Optimization - Optimize the equations Technology Mapping - Find circuit from equations and map to flip-flops and gate technology Verification - Verify correctness of final design Chapter 5 - Part 2 3

4 State Assignment Example Present Next State Output State x= x= x= x= A A B B A B How may assignments of codes with a minimum number of bits? Two A =, B = or A =, B = Does it make a difference? Only in variable inversion, so small, if any. Chapter 5 - Part 2 4

5 State Assignment Example 2 Present Next State Output State x= x= x= x= A A B B A C C D C D A B How may assignments of codes with a minimum number of bits? = 24 Does code assignment make a difference in cost? Chapter 5 - Part 2 5

6 State Assignment Example 2 (continued) Counting Order Assignment: A =, B =, C =, D = The resulting coded state table: Present State Next State x = x = Output x = x = Chapter 5 - Part 2 6

7 State Assignment Example 2 (continued) Gray Code Assignment: A =, B =, C =, D = The resulting coded state table: Present State Next State x = x = Output x = x = Chapter 5 - Part 2 7

8 Find Flip-Flop Input and Output Equations: Example 2 Counting Order Assignment Assume D flip-flops Interchange the bottom two rows of the state table, to obtain K-maps for D, D 2, and Z: D D 2 Z Y Y 2 Y Y 2 Y Y 2 Chapter 5 - Part 2 8

9 Optimization: Example 2: Counting Order Assignment Performing two-level optimization: D D 2 Z Y Y 2 Y Y 2 Y Y 2 D = Y Y 2 + Y Y 2 D 2 = Y Y 2 + Y Y 2 + Y Y 2 Z = Y Y 2 Gate Input Cost = 22 Chapter 5 - Part 2 9

10 Find Flip-Flop Input and Output Equations: Example 2 Gray Code Assignment Assume D flip-flops Obtain K-maps for D, D 2, and Z: D D 2 Z Y Y 2 Y Y 2 Y Y 2 Chapter 5 - Part 2

11 Optimization: Example 2: Assignment 2 Performing two-level optimization: D D 2 Z Y 2 Y Y 2 2 Y Y Y D = Y Y 2 + Y 2 Gate Input Cost = 9 D 2 = Select this state assignment to Z = Y Y 2 complete design in slide Chapter 5 - Part 2

12 One Flip-flop per State (One-Hot) Assignment Example codes for four states: (Y 3, Y 2, Y, Y ) =,,, and. In equations, need to include only the variable that is for the state, e. g., state with code, is represented in equations by Y instead of Y 3 Y 2 Y Y because all codes with or two or more s have don t care next state values. Provides simplified analysis and design Combinational logic may be simpler, but flipflop cost higher may or may not be lower cost Chapter 5 - Part 2 2

13 State Assignment Example 2 (continued) One-Hot Assignment : A =, B =, C =, D = The resulting coded state table: Present State Next State x = x = Output x = x = Chapter 5 - Part 2 3

14 Optimization: Example 2: One Hot Assignment Equations read from next state variable entries in table: D = (Y + Y + Y 3 ) or Y 2 D = (Y + Y 3 ) D 2 = (Y + Y 2 ) or (Y + Y 3 ) D 3 = Y 2 Z = Y 3 Gate Input Cost = 5 Combinational cost intermediate plus cost of two more flip-flops needed. Chapter 5 - Part 2 4

15 Map Technology Library: D Flip-flops with Reset (not inverted) NAND gates with up to 4 inputs and inverters Initial Circuit: D D C R Y Y 2 Z Clock Reset C R Chapter 5 - Part 2 5

16 Mapped Circuit - Final Result D Y C R Z D Y 2 Clock Reset C R Chapter 5 - Part 2 6

17 Sequential Design: Example Design a sequential modulo 3 accumulator for 2- bit operands Definitions: Modulo n adder - an adder that gives the result of the addition as the remainder of the sum divided by n Example: modulo 3 = remainder of 4/3 = Accumulator - a circuit that accumulates the sum of its input operands over time - it adds each input operand to the stored sum, which is initially. Stored sum: (Y,Y ), Input: (, ), Output: (Z,Z ) Chapter 5 - Part 2 7

18 Example (continued) Complete the state table Y Y Z Z Y (t+), Y (t+) Y (t+), Y (t+) State Assignment: (Y,Y ) = (Z,Z ) Y (t+), Y (t+) Y (t+), Y (t+) A () B () - () C () Codes are in gray code order to ease use of K-maps in the next step Chapter 5 - Part 2 8

19 Example (continued) Complete the state diagram: Reset C/ A/ B/ Chapter 5 - Part 2 9

20 Example (continued) Find optimized flip-flop input equations for D flip-flops D D Y Y Y Y D = D = Chapter 5 - Part 2 2

21 Circuit - Final Result with AND, OR, NOT D Y Z C R D Y Z Reset Clock C R Chapter 5 - Part 2 2

22 Other Flip-Flop Types J-K and T flip-flops Behavior Implementation Basic descriptors for understanding and using different flip-flop types Characteristic tables Characteristic equations Excitation tables For actual use, see Reading Supplement - Design and Analysis Using J-K and T Flip-Flops Chapter 5 - Part 2 22

23 J-K Flip-flop Behavior Same as S-R flip-flop with J analogous to S and K analogous to R Except that J = K = is allowed, and For J = K =, the flip-flop changes to the opposite state As a master-slave, has same s catching behavior as S-R flip-flop If the master changes to the wrong state, that state will be passed to the slave E.g., if master falsely set by J =, K = cannot reset it during the current clock cycle Chapter 5 - Part 2 23

24 J-K Flip-flop (continued) Implementation To avoid s catching behavior, one solution used is to use an edge-triggered D as the core of the flip-flop Symbol J K C J D K C Chapter 5 - Part 2 24

25 T Flip-flop Behavior Has a single input T For T =, no change to state For T =, changes to opposite state Same as a J-K flip-flop with J = K = T As a master-slave, has same s catching behavior as J-K flip-flop Cannot be initialized to a known state using the T input Reset (asynchronous or synchronous) essential Chapter 5 - Part 2 25

26 T Flip-flop (continued) Implementation To avoid s catching behavior, one solution used is to use an edge-triggered D as the core of the flip-flop Symbol T T D C C Chapter 5 - Part 2 26

27 Basic Flip-Flop Descriptors Used in analysis Characteristic table - defines the next state of the flip-flop in terms of flip-flop inputs and current state Characteristic equation - defines the next state of the flip-flop as a Boolean function of the flip-flop inputs and the current state Used in design Excitation table - defines the flip-flop input variable values as function of the current state and next state Chapter 5 - Part 2 27

28 D Flip-Flop Descriptors Characteristic Table D Q(t ) + Operation Reset Set Characteristic Equation Q(t+) = D Excitation Table Q(t +) D Operation Reset Set Chapter 5 - Part 2 28

29 T Flip-Flop Descriptors Characteristic Table T Q(t+ ) Operation Q(t) Q(t) No change Complement Characteristic Equation Q(t+) = T Q Excitation Table Q(t+) Q(t) Q(t) T Operation No change Complement Chapter 5 - Part 2 29

30 S-R Flip-Flop Descriptors Characteristic Table S Characteristic Equation Q(t+) = S + R Q, S. R = Excitation Table Q(t) R Q(t +) Q(t)? Q(t+) S Operation No change Reset Set Undefined R Operation No change Set Reset No change Chapter 5 - Part 2 3

31 J-K Flip-Flop Descriptors Characteristic Table Characteristic Equation Q(t+) = J Q + K Q Excitation Table J Q(t) K Q(t+) Q(t) Q(t) Q(t + ) J Operation No change Reset Set Complement K Operation No change Set Reset No Change Chapter 5 - Part 2 3

32 Flip-flop Behavior Example Use the characteristic tables to find the output waveforms for the flip-flops shown: Clock D,T D Q D C T Q T C Chapter 5 - Part 2 32

33 Flip-Flop Behavior Example (continued) Use the characteristic tables to find the output waveforms for the flip-flops shown: Clock S,J R,K S C R Q SR? J C K Q JK Chapter 5 - Part 2 33

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