PCIe: EYE DIAGRAM ANALYSIS IN HYPERLYNX

Transcription

1 PCIe: EYE DIAGRAM ANALYSIS IN HYPERLYNX w w w. m e n t o r. c o m

2 PCIe: Eye Diagram Analysis in HyperLynx PCI Express Tutorial This PCI Express tutorial will walk you through time-domain eye diagram analysis in HyperLynx. You will use the HyperLynx pre-layout planning tool, LineSim, to learn how you can use HyperLynx to characterize various design considerations of a PCI Express Gen1 interface. There will be three main topics of analysis: Analyzing loss on transmission lines in terms of db using the stackup editor Transmitter spec compliance using eye diagram analysis and eye masks Effects of loss on received eyes using eye diagram analysis and eye masks Open the Schematic After HyperLynx starts, click on the New icon, then click on icon New SI Schematic. Go to: Models > Edit Model Library Path, click on Edit, then Add button, and select path of: E:\HLv90_GHz_Channel_for_vlab\Channel_Lab1_PCIe\models. PCIe 1.0 Tutorial p. 1

3 Go to: File > Open Schematic and open the file 1_PCIe_Loss.ffs located in the directory: E:\HLv90_GHz_Channel_for_vlab\Channel_Lab1_PCIe\ (Select No to any intermediate message). You may find that the LineSim window is split horizontally so as to display transmission line and power plane windows. If so, you can minimize the power plane window and maximize the transmission line window. You can use the menu command View/Fit to window to center the channel in the display window; this command is also available as a button on the toolbar. Your HyperLynx window should now be similar to the one shown below. You will notice that this topology consists only of transmission lines. We are going to begin the lab by looking only at the loss characteristics of some board traces. PCIe 1.0 Tutorial p. 2

4 1. Click Setup to make sure Enable Lossy Simulation is checked. If it is not, check it. 2. Click on the Edit Stackup icon or go to Setup > Stackup. 3. In the Stackup Editor, click on the Custom View tab. PCIe 1.0 Tutorial p. 3

5 Notice that the Custom View tab has every column of interest to the stackup. This view can be customized to your needs. We are going to look at two different micrsostrip trace stackups and view the loss of those traces in the loss viewer. 4. Enlarge the Stackup Editor window so that it takes up most of the screen. Scroll all the way to the right. 5. Click View on top (row 2) in the Loss Curve column. 6. Click on the Attenuation button and make sure both Resistive and Dielectric are checked. PCIe 1.0 Tutorial p. 4

6 7. Zoom into the region around 1GHz. This can be done by using the cursor to draw a box to zoom in. You can also use the cursor to hover over points to see their values. Notice our loss, or attenuation, for the top layer stackup (which has a 3-mil trace width) is around 9.8 db/m at 1.25GHz. Since the data rate of PCI Express is 2.5Gbps, 1.25GHz is our primary frequency of interest here. Also notice that dielectric loss doesn t start to dominate until 3.536GHz. That is a strong indication that our stackup design is not optimized to get the least loss we want, given our dielectric material. 8. Close the Loss-vs-Frequency Graph. Notice that on Layer 12 (bottom), for the test width of 12 mils, the trace has the same impedance as for Layer 2, which only has a 3-mil trace width. This is due to the larger dielectric height between the bottom trace and its reference plane. The two traces have the same impedance but, as you will see, very different loss characteristics. 9. Click on the View on bottom (row 12) in the Loss Curve" column. 10. Zoom into the region around 1GHz. PCIe 1.0 Tutorial p. 5

7 Notice our attenuation for the bottom layer stackup (with the 12-mil trace width) is much lower - around 5.7 db/m at 1.25GHz. Also notice that dielectric loss starts to dominate at about 423MHz. With dielectric loss dominating through most of the frequency range, it is clear that we have made a stackup which does the best we can for loss given our dielectric material. 11. Close the Loss-vs-Frequency Graph. 12. Click on the Dielectric button and edit the Loss Tangent in row 11 to be PCIe 1.0 Tutorial p. 6

8 13. Go to the Customer View button then click again on View on bottom (row 12) in the Loss Curve column. 14. Zoom into the region around 1GHz. Our attenuation has now dropped to only about 4dB/m at 1.25GHz. Changing dielectric materials (and hence loss tangent) is another way to keep losses minimized. 15. Close the Loss-vs-Frequency Graph. 16. Click Cancel on the Stackup Editor. 17. Click yes to close the stackup editor without making changes (we don t want to make any changes). 18. Double-click on the transmission line TL1 in the main window. PCIe 1.0 Tutorial p. 7

9 19. Click on the Loss tab. 20. Zoom into the region around 1GHz. PCIe 1.0 Tutorial p. 8

10 This is another way to view the loss of a line. It calculates the loss given the actual line length, but notice there is a check box to display the loss per unit length, if so desired. Also notice that because we have a coupled differential pair, we can choose to examine the loss using differential or common mode propagation. The loss for this particular differential pair is extremely high around 15 db at 1.25GHz. The loss budget for PCI Express at 1.25 GHz is 13.2dB, so obviously this line will not work. 21. Click on the Edit Coupling Regions tab. Notice these traces are on the top layer.they are 3-mil traces (like we were looking at before) and the transmission line is 60 inches long. That is the reason for the excessive loss. 22. In the length field, edit the length of the transmission line to be 30 inches. PCIe 1.0 Tutorial p. 9

11 23. Click on the Loss tab again. The loss is now down at around 8dB at 1.25GHz. 24. Click Cancel to close the Edit Transmission Line box. 25. Now double-click on the transmission line TL3 in the main window. 26. Click on the Loss tab. PCIe 1.0 Tutorial p. 10

12 27. Zoom into the region around 1GHz. Notice the loss for this line is down at 4.5dB at 1.25GHz. 28. Click on the Edit Coupling Regions tab. This is the bottom-layer stackup from before, with the 12-mil traces. That is why it shows much better attenuation. 29. Click Cancel to close the Edit Transmission Line box. As you can see, the loss viewer is a useful tool for doing some general stackup and layout planning, which can be a great help early in the design cycle. It can be used to view the effects of varying both lengths and stackup. Simulation 30. Go to File > Open LineSim Schematic then click no to avoid saving changes and open 2_PCIe_Simulation_TXval.ffs. PCIe 1.0 Tutorial p. 11

13 31. Open the Oscilloscope by going to Simulate SI > Run Interactive Simulation (SI Oscilloscope ). 32. Select Eye Diagram mode under Operation and then click the Configure button. PCIe 1.0 Tutorial p. 12

14 33. Load a PRBS with bit order of 8. Make sure bit interval is set for 0.4ns, sequence repetitions set for 1, skip first 2 bits, and show 1 eye(s), with 0 jitter. 34. Click on the Eye Mask tab and load the PCIE_TX_transition eye mask. Click OK. PCIe 1.0 Tutorial p. 13

15 35. In the Oscilloscope, make sure Eye Mask is checked and set vertical position for 0mV and scale to 200mV/div. Set horizontal delay to 0.1ns and scale to 50ps/div. 36. Make sure that Typical is checked under IC modeling. 37. Select Insert diff probe under the Pins field; choose R1 and R2 as positive and negative pins, respectively; then click OK. PCIe 1.0 Tutorial p. 14

16 38. Click Start Simulation to view results. PCIe 1.0 Tutorial p. 15

17 39. Adjust the eye mask as necessary by clicking the Adjust Mask button and using cursor to drag the mask to center it horizontally in the eye. Do not adjust the mask vertically; make sure it is centered vertically about zero volts. The resulting waveform is very well-centered between the minimum and maximum regions of the eye mask. We can also take a look at the component variations, to see if it falls within the requirements. 40. Click on the Slow-Weak button under IC Modeling. Click on Erase to erase the current waveform. 41. Re-simulate. Adjust the eye mask as necessary. Now the following waveform is obtained. Notice that the slow/weak case still passes the minimum eye requirement. PCIe 1.0 Tutorial p. 16

18 42. Click on the Fast-Strong button under IC Modeling. Click Erase to erase the current waveform. 43. Re-simulate. Adjust the eye mask as necessary. Notice that the fast/strong case still passes the maximum voltage swing requirement. PCIe 1.0 Tutorial p. 17

19 44. Close the Oscilloscope. This part passes the transmitter specification; granted, this is a made-up part. It also does not have any de-emphasis enabled, which is also required by the specification. This will be discussed later in the lab. Now let s see how this transmitter performs in an actual topology. 45. Go to File > Open LineSim Schematic and then click no to avoid saving changes. Open 3_PCIe_Simulation_varTW.ffs. PCIe 1.0 Tutorial p. 18

20 46. Open the Oscilloscope by going to Simulate SI > Run Interactive Simulation (SI Oscilloscope ). 47. Select Eye Diagram mode under Operation. Then click the Configure button. 48. Load a PRBS with bit order of 8. Make sure bit interval is set for 0.4ns, sequence repetitions set for 1, skip first 20 bits, and show 1 eye(s), with 0 jitter. PCIe 1.0 Tutorial p. 19

21 49. Click on the Eye Mask tab and load the PCIE_RX eye mask. Click OK. PCIe 1.0 Tutorial p. 20

22 50. In the Oscilloscope, make sure Eye Mask is checked. Set vertical position for 0mV and scale to 200mV/div.; set horizontal delay to 0.35ns and scale to 50ps/div. 51. Make sure that Typical is checked under IC modeling. 52. Set R1.1 pin and R2.1 pin as differential probes (as in Step 37). 53. Click Start Simulation to view results. Adjust the eye mask as necessary to center it horizontally in the eye. Do not adjust the mask vertically; make sure it is centered vertically about zero volts. PCIe 1.0 Tutorial p. 21

23 The eye quality is very poor. That is because this is the lossy configuration that we analyzed before: the top-layer traces with the 3-mil trace width. The traces are 1 meter long. 54. Uncheck the current diff. probes. 55. Set R3.1 pin and R4.1 pin as differential probes (as in Step 37) 56. Change the horizontal delay to 0.2ns. 57. Click Start Simulation to view results. Adjust the eye mask as necessary. PCIe 1.0 Tutorial p. 22

24 The eye is dramatically improved. This is the topology with the bottom-side traces, which were 12 mils wide. The traces are also 1 meter long, but as you can see exhibit much less loss than the 3-mil traces and result in a much better eye. 58. Close the Oscilloscope. 59. Double-click on the transmission line TL1. Click on the Edit Coupling Regions tab. 60. Change the length to 10 inches. 61. Click OK. 62. Open the SI Oscilloscope. 63. Uncheck the R3.1/R4.1 probe and check the R1.1/R2.1 probe. 64. Change the horizontal delay to 0 ns. PCIe 1.0 Tutorial p. 23

25 PCIe: Eye Diagram Analysis in HyperLynx 65. Re-simulate the design with the modified trace length. Scrod the waveform left/right to display a full eye in center. Adjust the eye mask as necessary. This is also an acceptable eye. It uses the same lossy stackup as before, but because the line is only 10 inches in length, does not have excessive attenuation. This illustrates that it is possible to create passing designs with thinner traces, provided the route lengths are sufficiently short. 66. Close the Oscilloscope. Summary This tutorial demonstrates how to study basic behavior of your PCIe 2.0 channel designs. This was performed in the pre-layout environment, LineSim, but the same type of analysis can be performed on the routed channel design on a single board or through multiple boards in the post layout tool, BoardSim. This allows you to validate that the routed channel meets the design intent prior to creating your prototype. To learn more about additional capabilities in the HyperLynx SI tool suite, go to: For the latest product information, call us or visit: w w w. m e n t o r. c o m 2012 Mentor Graphics Corporation, all rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation and may be duplicated in whole or in part by the original recipient for internal business purposes only, provided that this entire notice appears in all copies. In accepting this document, the recipient agrees to make every reasonable effort to prevent unauthorized use of this information. All trademarks mentioned in this document are the trademarks of their respective owners. LVG 12_13 misc 1830-W