Power-Optimal Pipelining in Deep Submicron Technology
|
|
- Gavin Shaw
- 5 years ago
- Views:
Transcription
1 ISLPED /10/2004 -Optimal Pipelining in Deep Submicron Technology Seongmoo Heo and Krste Asanovi Computer Architecture Group, MIT CSAIL
2 Traditional Pipelining Goal: Maximum performance Vdd Clk-Q Setup Propagation Delay Clk Clk Clk
3 Pipelining as a Low- Tool Goal: Low-, Fixed Throughput Vdd Clk-Q Setup Propagation Delay Clk Time Slack Clk Time Slack Clk
4 Pipelining as a Low- Tool Goal: Low-, Fixed Throughput Vdd Clk-Q Setup Propagation Delay Clk Time Slack Traded for (supply voltage scaling) Clk Time Slack Clk
5 Pipelining as a Low- Tool * Clock frequency fixed Flip-flop Overhead Pipelining Time slack Delay
6 Pipelining as a Low- Tool * Clock frequency fixed Supply voltage scaling Saving Delay
7 -Optimal Pipelining reduction from pipelining limited by power overhead of increased number of flip-flops -Optimal Pipelining
8 -Optimal Pipelining reduction from pipelining limited by power overhead of increased number of flip-flops -Optimal Pipelining Too shallow pipelining Delay
9 -Optimal Pipelining reduction from pipelining limited by power overhead of increased number of flip-flops -Optimal Pipelining Too deep pipelining Too shallow pipelining Delay
10 -Optimal Pipelining reduction from pipelining limited by power overhead of increased number of flip-flops -Optimal Pipelining Too deep pipelining Optimal pipelining Too shallow pipelining Optimal Saving Delay
11 Pipelining is an old idea. Contribution Research focus has been on performance impact of pipelining. Idea of using pipelining [Chandrakasan 92] to lower power has not been fully explored in deep submicron technology. Analysis and circuit-level simulation of -Optimal Pipelining for different regimes of V th, activity factor, clock gating
12 Bottom-to-Top Approach 1. Impact of pipelining on power component 2. Impact of pipelining on total power (with/without clock-gating) Total (clock-gated) active inactive active Time Switching Component Leakage Component Idle Component
13 Bottom-to-Top Approach 1. Impact of pipelining on power component 2. Impact of pipelining on total power (with/without clock-gating) Total (not clock-gated) Switching Component Leakage Component active inactive active Idle Component Time *Idle power = power consumed when circuit is idle and not clock-gated
14 Target digital system: Fixed throughput, Highly parallel computation, Logic-dominant Test bench TG flip-flops Methodology BPTM (Berkeley Predictive Technology Model) 70nm process: LVT(0.17/-0.2), MVT(0.19/-0.22), HVT(0.21/-0.24) Hspice simulation at 100 C, Clock = 2 GHz Baseline N FO4 inverters (N = 2 ~ 24) TG flip-flops One Pipeline Stage
15 Pipelining and Switching : Analytical Trend Switching Optimal Saving Flip-flop overhead O(1/N) Optimal FO4 O(N 2 ) Quadratic reduction of logic switching power V 2 dd N 2 Number of FO4 per stage, N
16 Pipelining and Leakage : Analytical Trend Leakage Optimal Saving O(1/N) Flip-flop overhead Optimal FO4 O(N α ) (1<α< 2) Superlinear reduction of logic leakage power V dd * e(ηv dd ) N α DIBL effect Number of FO4 per stage, N
17 Pipelining and Idle : Analytical Trend Clock-gating is not always possible Increased control complexity insufficient setup time of clock enable signal Leakage + Flip-flop Switching Between leakage power scaling and flip-flop switching power scaling depending on leakage level
18 Relative Pipelining and Idle : Leakage Scale Optimal Saving Optimal FO4 O(1/N) Analytical Trend O(N α ) (1<α< 2) Idle Optimal FO4 Flip-flop Switching Scale O(1/N) Optimal Saving O(N) Linear reduction of Flip-flop switching power 1/N * V dd 2 N Number of FO4 per stage, N Number of FO4 per stage, N
19 Fixed 2 GHz Components Simulation Results: Components Switching Leakage Idle Right hand side curve O(N 2 ) O(N α ) (1<α< 2) O(N) or O(N α ) (1<α< 2) Saving* 79(HVT)~ 82(LVT)% 70(LVT)~ 75(HVT)% 55(HVT)~ 70(LVT)% N* N = Number of FO4 inverters per stage N* = Optimal N Saving* = Optimal power saving by pipelining (Not including flip-flop delay)
20 Optimal Saving Optimal FO4 = 6 Clock Gating Optimal FO4 = 6~8 No Clock Gating relative power relative power *2 GHz *Flip-flop delay not included in optimal FO4 activity factor activity factor
21 Optimal Saving Optimal FO4 = 6 Optimal FO4 = 6~8 Clock Gating Idle No Clock Gating relative power Leakage relative power Switching Switching activity factor activity factor
22 Optimal Saving Optimal FO4 = 6 Optimal FO4 = 6~8 Clock Gating No Clock Gating relative power relative power LVT activity factor activity factor
23 Discussion LVT can be fast and power-efficient enables lower V dd Flip-flop delay more important than flip-flop power for power-optimal pipelining
24 Limitation of This Work Super-linear growth of flip-flops Additional memory Reduced glitches Parasitic wire capacitance Effect on optimal logic depth Effect on optimal power saving
25 Conclusion Pipelining is an effective low-power tool when used to support voltage scaling in digital system implementing highly parallel computation. Optimal Logic Depth: 6-8 FO4 ~ 8-10 FO4 including flip-flop delay Optimal Saving: 55 80% It depends on V th, AF, Clock-Gating Insights: Pipelining is more effective with High AF Pipelining is most effective at saving switching power Pipelining is more effective with lower V th Except for when leakage power is dominant. Pipelining is more effective with clock-gating reduced flip-flop overhead.
26 Acknowledgments Thanks to SCALE group members and anonymous reviewers Funded by NSF CAREER award CCR , NSF ITR award CCR , and a donation from Intel Corporation.
27 BACKUP SLIDES
Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction
Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Reduction Stephanie Augsburger 1, Borivoje Nikolić 2 1 Intel Corporation, Enterprise Processors Division, Santa Clara, CA, USA. 2 Department
More informationMASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Science
MASSACHUSETTS INSTITUTE OF TECHNOLOGY epartment of Electrical Engineering and Computer Science 6.374: Analysis and esign of igital Integrated Circuits Problem Set # 5 Fall 2003 Issued: 10/28/03 ue: 11/12/03
More informationEE-382M VLSI II FLIP-FLOPS
EE-382M VLSI II FLIP-FLOPS Gian Gerosa, Intel Fall 2008 EE 382M Class Notes Page # 1 / 31 OUTLINE Trends LATCH Operation FLOP Timing Diagrams & Characterization Transfer-Gate Master-Slave FLIP-FLOP Merged
More informationPOWER OPTIMIZED CLOCK GATED ALU FOR LOW POWER PROCESSOR DESIGN
POWER OPTIMIZED CLOCK GATED ALU FOR LOW POWER PROCESSOR DESIGN 1 L.RAJA, 2 Dr.K.THANUSHKODI 1 Prof., Department of Electronics and Communication Engineeering, Angel College of Engineering and Technology,
More informationEEC 118 Lecture #9: Sequential Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #9: Sequential Logic Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Outline Review: Static CMOS Logic Finish Static CMOS transient analysis Sequential
More informationII. ANALYSIS I. INTRODUCTION
Characterizing Dynamic and Leakage Power Behavior in Flip-Flops R. Ramanarayanan, N. Vijaykrishnan and M. J. Irwin Dept. of Computer Science and Engineering Pennsylvania State University, PA 1682 Abstract
More informationPerformance Driven Reliable Link Design for Network on Chips
Performance Driven Reliable Link Design for Network on Chips Rutuparna Tamhankar Srinivasan Murali Prof. Giovanni De Micheli Stanford University Outline Introduction Objective Logic design and implementation
More informationLow Power Approach of Clock Gating in Synchronous System like FIFO: A Novel Clock Gating Approach and Comparative Analysis
Low Power Approach of Clock Gating in Synchronous System like FIFO: A Novel Clock Gating Approach and Comparative Analysis Abstract- A new technique of clock is presented to reduce dynamic power consumption.
More informationdata and is used in digital networks and storage devices. CRC s are easy to implement in binary
Introduction Cyclic redundancy check (CRC) is an error detecting code designed to detect changes in transmitted data and is used in digital networks and storage devices. CRC s are easy to implement in
More informationDesign of Low Power Universal Shift Register
Design of Low Power Universal Shift Register 1 Saranya.M, 2 V.Vijayakumar, 3 T.Ravi, 4 V.Kannan 1 M.Tech-VLSI design, Sathyabama University, Jeppiaar Nagar, Rajiv Gandhi Salai, Chennai 119 2 Assistant
More informationEEC 116 Fall 2011 Lab #5: Pipelined 32b Adder
EEC 116 Fall 2011 Lab #5: Pipelined 32b Adder Dept. of Electrical and Computer Engineering University of California, Davis Issued: November 2, 2011 Due: November 16, 2011, 4PM Reading: Rabaey Sections
More informationA Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application
A Novel Low-overhead elay Testing Technique for Arbitrary Two-Pattern Test Application Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, and Kaushik Roy School of Electrical and Computer Engineering,
More informationDigital System Clocking: High-Performance and Low-Power Aspects
igital ystem Clocking: High-Performance and Low-Power Aspects Vojin G. Oklobdzija, Vladimir M. tojanovic, ejan M. Markovic, Nikola M. Nedovic Chapter 8: tate-of-the-art Clocked torage Elements in CMO Technology
More informationSimultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits
Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits Youngsoo Shin 1, Sewan Heo 1, Hyung-Ock Kim 1, Jung Yun Choi 2 1 Dept. of Electrical Engineering, KAIST, KOREA
More informationDigital Integrated Circuits EECS 312. Review. Remember the ENIAC? IC ENIAC. Trend for one company. First microprocessor
14 12 10 8 6 IBM ES9000 Bipolar Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CDC Cyber 205 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(DSIP)
More informationDigital Integrated Circuits EECS 312
14 12 10 8 6 Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CDC Cyber 205 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(DSIP) 0 1950 1960 1970 1980
More informationDual Edge Adaptive Pulse Triggered Flip-Flop for a High Speed and Low Power Applications
International Journal of Scientific and Research Publications, Volume 5, Issue 10, October 2015 1 Dual Edge Adaptive Pulse Triggered Flip-Flop for a High Speed and Low Power Applications S. Harish*, Dr.
More informationAN EFFICIENT LOW POWER DESIGN FOR ASYNCHRONOUS DATA SAMPLING IN DOUBLE EDGE TRIGGERED FLIP-FLOPS
AN EFFICIENT LOW POWER DESIGN FOR ASYNCHRONOUS DATA SAMPLING IN DOUBLE EDGE TRIGGERED FLIP-FLOPS NINU ABRAHAM 1, VINOJ P.G 2 1 P.G Student [VLSI & ES], SCMS School of Engineering & Technology, Cochin,
More informationTiming Error Detection: An Adaptive Scheme To Combat Variability EE241 Final Report Nathan Narevsky and Richard Ott {nnarevsky,
Timing Error Detection: An Adaptive Scheme To Combat Variability EE241 Final Report Nathan Narevsky and Richard Ott {nnarevsky, tomott}@berkeley.edu Abstract With the reduction of feature sizes, more sources
More informationINTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) Design and Analysis of CNTFET Based D Flip-Flop
INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 6464(Print)
More informationLoad-Sensitive Flip-Flop Characterization
Appears in IEEE Workshop on VLSI, Orlando, Florida, April Load-Sensitive Flip-Flop Characterization Seongmoo Heo and Krste Asanović Massachusetts Institute of Technology Laboratory for Computer Science
More informationECE 555 DESIGN PROJECT Introduction and Phase 1
March 15, 1998 ECE 555 DESIGN PROJECT Introduction and Phase 1 Charles R. Kime Dept. of Electrical and Computer Engineering University of Wisconsin Madison Phase I Due Wednesday, March 24; One Week Grace
More informationSGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor
LETTER IEICE Electronics Express, Vol.14, No.8, 1 12 SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor Taotao Zhu 1, Xiaoyan Xiang 2a), Chen Chen 2, and
More informationECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2011
ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2011 Lecture 9: TX Multiplexer Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements & Agenda Next
More informationPerformance Modeling and Noise Reduction in VLSI Packaging
Performance Modeling and Noise Reduction in VLSI Packaging Ph.D. Defense Brock J. LaMeres University of Colorado October 7, 2005 October 7, 2005 Performance Modeling and Noise Reduction in VLSI Packaging
More informationLFSR Counter Implementation in CMOS VLSI
LFSR Counter Implementation in CMOS VLSI Doshi N. A., Dhobale S. B., and Kakade S. R. Abstract As chip manufacturing technology is suddenly on the threshold of major evaluation, which shrinks chip in size
More informationDesign and analysis of RCA in Subthreshold Logic Circuits Using AFE
Design and analysis of RCA in Subthreshold Logic Circuits Using AFE 1 MAHALAKSHMI M, 2 P.THIRUVALAR SELVAN PG Student, VLSI Design, Department of ECE, TRPEC, Trichy Abstract: The present scenario of the
More informationECE321 Electronics I
ECE321 Electronics I Lecture 25: Sequential Logic: Flip-flop Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: pzarkesh.unm.edu Slide: 1 Review of Last
More informationA Novel Approach for Auto Clock Gating of Flip-Flops
A Novel Approach for Auto Clock Gating of Flip-Flops Kakarla Sandhya Rani 1, Krishna Prasad Satamraju 2 1 P.G Scholar, Department of ECE, Vasireddy Venkatadri Institute of Technology, Nambur, Guntur (dt),
More informationEL302 DIGITAL INTEGRATED CIRCUITS LAB #3 CMOS EDGE TRIGGERED D FLIP-FLOP. Due İLKER KALYONCU, 10043
EL302 DIGITAL INTEGRATED CIRCUITS LAB #3 CMOS EDGE TRIGGERED D FLIP-FLOP Due 16.05. İLKER KALYONCU, 10043 1. INTRODUCTION: In this project we are going to design a CMOS positive edge triggered master-slave
More informationAsynchronous (Ripple) Counters
Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory. The chapter about flip-flops introduced
More informationDESIGN AND SIMULATION OF A CIRCUIT TO PREDICT AND COMPENSATE PERFORMANCE VARIABILITY IN SUBMICRON CIRCUIT
DESIGN AND SIMULATION OF A CIRCUIT TO PREDICT AND COMPENSATE PERFORMANCE VARIABILITY IN SUBMICRON CIRCUIT Sripriya. B.R, Student of M.tech, Dept of ECE, SJB Institute of Technology, Bangalore Dr. Nataraj.
More informationLOW POWER LEVEL CONVERTING FLIP-FLOP DESIGN BY USING CONDITIONAL DISCHARGE TECHNIQUE
LOW POWER LEVEL CONVERTING FLIP-FLOP DESIGN BY USING CONDITIONAL DISCHARGE TECHNIQUE Keerthana S Assistant Professor, Department of Electronics and Telecommunication Engineering Karpagam College of Engineering
More informationRAZOR: CIRCUIT-LEVEL CORRECTION OF TIMING ERRORS FOR LOW-POWER OPERATION
RAZOR: CIRCUIT-LEVEL CORRECTION OF TIMING ERRORS FOR LOW-POWER OPERATION Shohaib Aboobacker TU München 22 nd March 2011 Based on Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation Dan
More informationDESIGN OF LOW POWER TEST PATTERN GENERATOR
International Journal of Electronics, Communication & Instrumentation Engineering Research and Development (IJECIERD) ISSN(P): 2249-684X; ISSN(E): 2249-7951 Vol. 4, Issue 1, Feb 2014, 59-66 TJPRC Pvt.
More informationClock Gating Aware Low Power ALU Design and Implementation on FPGA
Clock Gating Aware Low ALU Design and Implementation on FPGA Bishwajeet Pandey and Manisha Pattanaik Abstract This paper deals with the design and implementation of a Clock Gating Aware Low Arithmetic
More informationUniversity College of Engineering, JNTUK, Kakinada, India Member of Technical Staff, Seerakademi, Hyderabad
Power Analysis of Sequential Circuits Using Multi- Bit Flip Flops Yarramsetti Ramya Lakshmi 1, Dr. I. Santi Prabha 2, R.Niranjan 3 1 M.Tech, 2 Professor, Dept. of E.C.E. University College of Engineering,
More informationDESIGN OF DOUBLE PULSE TRIGGERED FLIP-FLOP BASED ON SIGNAL FEED THROUGH SCHEME
Scientific Journal Impact Factor (SJIF): 1.711 e-issn: 2349-9745 p-issn: 2393-8161 International Journal of Modern Trends in Engineering and Research www.ijmter.com DESIGN OF DOUBLE PULSE TRIGGERED FLIP-FLOP
More informationNovel Low Power and Low Transistor Count Flip-Flop Design with. High Performance
Novel Low Power and Low Transistor Count Flip-Flop Design with High Performance Imran Ahmed Khan*, Dr. Mirza Tariq Beg Department of Electronics and Communication, Jamia Millia Islamia, New Delhi, India
More informationDesign and Evaluation of a Low-Power UART-Protocol Deserializer
1 Design and Evaluation of a Low-Power UART-Protocol Deserializer Casey T. Morrison, William Goh, Saeed Sadrameli, and Eric Blattler Abstract The and evaluation of a low-power Universal Asynchronous Receiver/Transmitter
More informationBuilt-In Proactive Tuning System for Circuit Aging Resilience
IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems Built-In Proactive Tuning System for Circuit Aging Resilience Nimay Shah 1, Rupak Samanta 1, Ming Zhang 2, Jiang Hu 1, Duncan
More informationHigh Performance Dynamic Hybrid Flip-Flop For Pipeline Stages with Methodical Implanted Logic
High Performance Dynamic Hybrid Flip-Flop For Pipeline Stages with Methodical Implanted Logic K.Vajida Tabasum, K.Chandra Shekhar Abstract-In this paper we introduce a new high performance dynamic hybrid
More informationA Low-Power CMOS Flip-Flop for High Performance Processors
A Low-Power CMOS Flip-Flop for High Performance Processors Preetisudha Meher, Kamala Kanta Mahapatra Dept. of Electronics and Telecommunication National Institute of Technology Rourkela, India Preetisudha1@gmail.com,
More informationDigital System Design
Digital System Design by Dr. Lesley Shannon Email: lshannon@ensc.sfu.ca Course Website: http://www.ensc.sfu.ca/~lshannon/courses/ensc350 Simon Fraser University Slide Set: 8 Date: February 9, 2009 Timing
More informationA NOVEL DESIGN OF COUNTER USING TSPC D FLIP-FLOP FOR HIGH PERFORMANCE AND LOW POWER VLSI DESIGN APPLICATIONS USING 45NM CMOS TECHNOLOGY
A NOVEL DESIGN OF COUNTER USING TSPC D FLIP-FLOP FOR HIGH PERFORMANCE AND LOW POWER VLSI DESIGN APPLICATIONS USING 45NM CMOS TECHNOLOGY Ms. Chaitali V. Matey 1, Ms. Shraddha K. Mendhe 2, Mr. Sandip A.
More information55:131 Introduction to VLSI Design Project #1 -- Fall 2009 Counter built from NAND gates, timing Due Date: Friday October 9, 2009.
55:131 Introduction to VLSI Design Project #1 -- Fall 2009 Counter built from NAND gates, timing Due Date: Friday October 9, 2009 Introduction In this project we will create a transistor-level model of
More informationRetiming Sequential Circuits for Low Power
Retiming Sequential Circuits for Low Power José Monteiro, Srinivas Devadas Department of EECS MIT, Cambridge, MA Abhijit Ghosh Mitsubishi Electric Research Laboratories Sunnyvale, CA Abstract Switching
More informationDesign and Analysis of Custom Clock Buffers and a D Flip-Flop for Low Swing Clock Distribution Networks. A Thesis presented.
Design and Analysis of Custom Clock Buffers and a D Flip-Flop for Low Swing Clock Distribution Networks A Thesis presented by Mallika Rathore to The Graduate School in Partial Fulfillment of the Requirements
More informationSlack Redistribution for Graceful Degradation Under Voltage Overscaling
Slack Redistribution for Graceful Degradation Under Voltage Overscaling Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar and John Sartori VLSI CAD LABORATORY, UCSD PASSAT GROUP, UIUC UCSD VLSI CAD Laboratory
More informationMore on Flip-Flops Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <98> 98
More on Flip-Flops Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 98 Review: Bit Storage SR latch S (set) Q R (reset) Level-sensitive SR latch S S1 C R R1 Q D C S R D latch Q
More informationDesign and Analysis of a Linear Feedback Shift Register with Reduced Leakage Power
Design and Analysis of a Linear Feedback Shift Register with Reduced Leakage Power M. Janaki Rani Research scholar, Sathyabama University, Chennai, India S. Malarkkan Principal, ManakulaVinayagar Institute
More informationResearch Article Power Consumption and BER of Flip-Flop Inserted Global Interconnect
Hindawi Publishing Corporation VLSI Design Volume 7, Article ID 489, 9 pages doi:.55/7/489 Research Article Power Consumption and BER of Flip-Flop Inserted Global Interconnect Jingye Xu, Abinash Roy, and
More informationDesign of a Low Power Four-Bit Binary Counter Using Enhancement Type Mosfet
Design of a Low Power Four-Bit Binary Counter Using Enhancement Type Mosfet Praween Sinha Department of Electronics & Communication Engineering Maharaja Agrasen Institute Of Technology, Rohini sector -22,
More informationESE 570 STATIC SEQUENTIAL CMOS LOGIC CELLS. Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
ESE 570 STATIC SEQUENTIAL CMOS LOGIC CELLS 1 Classes of Logic Circuits two stable op. pts. Latch level triggered. Flip-Flop edge triggered. one stable op. pt. One-shot single pulse output no stable op.
More informationDesign of Low Power D-Flip Flop Using True Single Phase Clock (TSPC)
Design of Low Power D-Flip Flop Using True Single Phase Clock (TSPC) Swetha Kanchimani M.Tech (VLSI Design), Mrs.Syamala Kanchimani Associate Professor, Miss.Godugu Uma Madhuri Assistant Professor, ABSTRACT:
More informationAsynchronous Data Sampling Within Clock-Gated Double Edge-Triggered Flip-Flops
Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology IJCSMC, Vol. 4, Issue. 4, April 2015,
More informationStatic Timing Analysis for Nanometer Designs
J. Bhasker Rakesh Chadha Static Timing Analysis for Nanometer Designs A Practical Approach 4y Spri ringer Contents Preface xv CHAPTER 1: Introduction / 1.1 Nanometer Designs 1 1.2 What is Static Timing
More informationPICOSECOND TIMING USING FAST ANALOG SAMPLING
PICOSECOND TIMING USING FAST ANALOG SAMPLING H. Frisch, J-F Genat, F. Tang, EFI Chicago, Tuesday 6 th Nov 2007 INTRODUCTION In the context of picosecond timing, analog detector pulse sampling in the 10
More informationDUAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH LOW POWER CONSUMPTION
DUAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH LOW POWER CONSUMPTION Chien-Cheng Yu 1, 2 and Ching-Chith Tsai 1 1 Department of Electrical Engineering, National Chung-Hsing University, Taichung, Taiwan 2 Department
More informationISSN:
191 Low Power Test Pattern Generator Using LFSR and Single Input Changing Generator (SICG) for BIST Applications A K MOHANTY 1, B P SAHU 2, S S MAHATO 3 Department of Electronics and Communication Engineering,
More informationFigure.1 Clock signal II. SYSTEM ANALYSIS
International Journal of Advances in Engineering, 2015, 1(4), 518-522 ISSN: 2394-9260 (printed version); ISSN: 2394-9279 (online version); url:http://www.ijae.in RESEARCH ARTICLE Multi bit Flip-Flop Grouping
More informationP.Akila 1. P a g e 60
Designing Clock System Using Power Optimization Techniques in Flipflop P.Akila 1 Assistant Professor-I 2 Department of Electronics and Communication Engineering PSR Rengasamy college of engineering for
More informationSYNCHRONOUS DERIVED CLOCK AND SYNTHESIS OF LOW POWER SEQUENTIAL CIRCUITS *
SYNCHRONOUS DERIVED CLOCK AND SYNTHESIS OF LOW POWER SEUENTIAL CIRCUITS * Wu Xunwei (Department of Electronic Engineering Hangzhou University Hangzhou 328) ing Wu Massoud Pedram (Department of Electrical
More information12-bit Wallace Tree Multiplier CMPEN 411 Final Report Matthew Poremba 5/1/2009
12-bit Wallace Tree Multiplier CMPEN 411 Final Report Matthew Poremba 5/1/2009 Project Overview This project was originally titled Fast Fourier Transform Unit, but due to space and time constraints, the
More informationResearch Article Ultra Low Power, High Performance Negative Edge Triggered ECRL Energy Recovery Sequential Elements with Power Clock Gating
Research Journal of Applied Sciences, Engineering and Technology 7(16): 3312-3319, 2014 DOI:10.19026/rjaset.7.676 ISSN: 2040-7459; e-issn: 2040-7467 2014 Maxwell Scientific Publication Corp. Submitted:
More informationNew Single Edge Triggered Flip-Flop Design with Improved Power and Power Delay Product for Low Data Activity Applications
American-Eurasian Journal of Scientific Research 8 (1): 31-37, 013 ISSN 1818-6785 IDOSI Publications, 013 DOI: 10.589/idosi.aejsr.013.8.1.8366 New Single Edge Triggered Flip-Flop Design with Improved Power
More informationAN EFFICIENT DOUBLE EDGE TRIGGERING FLIP FLOP (MDETFF)
AN EFFICIENT DOUBLE EDGE TRIGGERING FLIP FLOP (MDETFF) S.Santhoshkumar, L.Saranya 2 (UG Scholar, Dept.of.ECE, Christ the king Engineering college, Tamilnadu, India, santhosh29ece@gmail.com) 2 (Asst. Professor,
More informationInternational Journal of Computer Trends and Technology (IJCTT) volume 24 Number 2 June 2015
Power and Area analysis of Flip Flop using different s Neha Thapa 1, Dr. Rajesh Mehra 2 1 ME student, Department of E.C.E, NITTTR, Chandigarh, India 2 Associate Professor, Department of E.C.E, NITTTR,
More informationSharif University of Technology. SoC: Introduction
SoC Design Lecture 1: Introduction Shaahin Hessabi Department of Computer Engineering System-on-Chip System: a set of related parts that act as a whole to achieve a given goal. A system is a set of interacting
More informationCHAPTER 4 RESULTS & DISCUSSION
CHAPTER 4 RESULTS & DISCUSSION 3.2 Introduction This project aims to prove that Modified Baugh-Wooley Two s Complement Signed Multiplier is one of the high speed multipliers. The schematic of the multiplier
More informationSequencing. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall,
Sequencing ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2013 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines Introduction Sequencing
More informationFinFET-Based Low-Swing Clocking
FinFET-Based Low-Swing Clocking CAN SITIK, Drexel University EMRE SALMAN, Stony Brook University LEO FILIPPINI, Drexel University SUNG JUN YOON, Stony Brook University BARIS TASKIN, Drexel University A
More informationEET2411 DIGITAL ELECTRONICS
5-8 Clocked D Flip-FlopFlop One data input. The output changes to the value of the input at either the positive going or negative going clock trigger. May be implemented with a J-K FF by tying the J input
More informationDesign of a High Frequency Dual Modulus Prescaler using Efficient TSPC Flip Flop using 180nm Technology
Design of a High Frequency Dual Modulus Prescaler using Efficient TSPC Flip Flop using 180nm Technology Divya shree.m 1, H. Venkatesh kumar 2 PG Student, Dept. of ECE, Nagarjuna College of Engineering
More informationDesign And Analysis of Clocked Subsystem Elements Using Leakage Reduction Technique
Design And Analysis of Clocked Subsystem Elements Using Leakage Reduction Technique Sanjay Singh, S.K. Singh, Mahesh Kumar Singh, Raj Kumar Sagar Abstract As the density and operating speed of CMOS VLSI
More informationDesign of Fault Coverage Test Pattern Generator Using LFSR
Design of Fault Coverage Test Pattern Generator Using LFSR B.Saritha M.Tech Student, Department of ECE, Dhruva Institue of Engineering & Technology. Abstract: A new fault coverage test pattern generator
More informationEECS150 - Digital Design Lecture 17 - Circuit Timing. Performance, Cost, Power
EECS150 - Digital Design Lecture 17 - Circuit Timing March 10, 2011 John Wawrzynek Spring 2011 EECS150 - Lec16-timing Page 1 Performance, Cost, Power How do we measure performance? operations/sec? cycles/sec?
More informationDigital Integrated Circuits EECS 312
14 12 10 8 6 Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CDC Cyber 205 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(DSIP) 0 1950 1960 1970 1980
More informationArea Efficient Pulsed Clock Generator Using Pulsed Latch Shift Register
International Journal for Modern Trends in Science and Technology Volume: 02, Issue No: 10, October 2016 http://www.ijmtst.com ISSN: 2455-3778 Area Efficient Pulsed Clock Generator Using Pulsed Latch Shift
More informationTutorial Outline. Design Levels
Tutorial Outline 8:3-8:45 8:45-9:5 9:5-9:3 9:3-1:3 1:3-1:5 1:5-12:15 12:15-1:3 1:3-2:3 2:3-3:3 3:3-3:5 3:5-4:3 4:3-4:45 Introduction and motivation Sources of power in CMOS designs Power analysis tools
More informationReport on 4-bit Counter design Report- 1, 2. Report on D- Flipflop. Course project for ECE533
Report on 4-bit Counter design Report- 1, 2. Report on D- Flipflop Course project for ECE533 I. Objective: REPORT-I The objective of this project is to design a 4-bit counter and implement it into a chip
More informationDESIGN OF A NEW MODIFIED CLOCK GATED SENSE-AMPLIFIER FLIP-FLOP
DESIGN OF A NEW MODIFIED CLOCK GATED SENSE-AMPLIFIER FLIP-FLOP P.MANIKANTA, DR. R. RAMANA REDDY ABSTRACT In this paper a new modified explicit-pulsed clock gated sense-amplifier flip-flop (MCG-SAFF) is
More informationEECS150 - Digital Design Lecture 18 - Circuit Timing (2) In General...
EECS150 - Digital Design Lecture 18 - Circuit Timing (2) March 17, 2010 John Wawrzynek Spring 2010 EECS150 - Lec18-timing(2) Page 1 In General... For correct operation: T τ clk Q + τ CL + τ setup for all
More informationLOW POWER AND HIGH PERFORMANCE SHIFT REGISTERS USING PULSED LATCH TECHNIQUE
OI: 10.21917/ijme.2018.0088 LOW POWER AN HIGH PERFORMANCE SHIFT REGISTERS USING PULSE LATCH TECHNIUE Vandana Niranjan epartment of Electronics and Communication Engineering, Indira Gandhi elhi Technical
More informationCHAPTER 6 DESIGN OF HIGH SPEED COUNTER USING PIPELINING
149 CHAPTER 6 DESIGN OF HIGH SPEED COUNTER USING PIPELINING 6.1 INTRODUCTION Counters act as important building blocks of fast arithmetic circuits used for frequency division, shifting operation, digital
More informationOn the Rules of Low-Power Design
On the Rules of Low-Power Design (and How to Break Them) Prof. Todd Austin Advanced Computer Architecture Lab University of Michigan austin@umich.edu Once upon a time 1 Rules of Low-Power Design P = acv
More informationLow Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur
Low Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture No. # 29 Minimizing Switched Capacitance-III. (Refer
More informationPERFORMANCE ANALYSIS OF AN EFFICIENT PULSE-TRIGGERED FLIP FLOPS FOR ULTRA LOW POWER APPLICATIONS
Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology ISSN 2320 088X IMPACT FACTOR: 5.258 IJCSMC,
More informationModifying the Scan Chains in Sequential Circuit to Reduce Leakage Current
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 3, Issue 1 (Sep. Oct. 2013), PP 01-09 e-issn: 2319 4200, p-issn No. : 2319 4197 Modifying the Scan Chains in Sequential Circuit to Reduce Leakage
More informationEfficient Architecture for Flexible Prescaler Using Multimodulo Prescaler
Efficient Architecture for Flexible Using Multimodulo G SWETHA, S YUVARAJ Abstract This paper, An Efficient Architecture for Flexible Using Multimodulo is an architecture which is designed from the proposed
More informationChapter 7 Sequential Circuits
Chapter 7 Sequential Circuits Jin-Fu Li Advanced Reliable Systems (ARES) Lab. epartment of Electrical Engineering National Central University Jungli, Taiwan Outline Latches & Registers Sequencing Timing
More informationPower Distribution and Clock Design
Lecture 3 Power Distribution and Clock Design R. Saleh Dept. of ECE University of British Columbia res@ece.ubc.ca 1 Overview of Lecture Power distribution in the past was a fairly simple task Goal of power
More informationAn FPGA Implementation of Shift Register Using Pulsed Latches
An FPGA Implementation of Shift Register Using Pulsed Latches Shiny Panimalar.S, T.Nisha Priscilla, Associate Professor, Department of ECE, MAMCET, Tiruchirappalli, India PG Scholar, Department of ECE,
More informationChapter 6. Flip-Flops and Simple Flip-Flop Applications
Chapter 6 Flip-Flops and Simple Flip-Flop Applications Basic bistable element It is a circuit having two stable conditions (states). It can be used to store binary symbols. J. C. Huang, 2004 Digital Logic
More informationPower Optimization of Linear Feedback Shift Register (LFSR) using Power Gating
Power Optimization of Linear Feedback Shift Register (LFSR) using Rebecca Angela Fernandes 1, Niju Rajan 2 1Student, Dept. of E&C Engineering, N.M.A.M Institute of Technology, Karnataka, India 2Assistant
More informationDESIGN AND ANALYSIS OF ADDER CIRCUITS USING LEAR SLEEP TECHNIQUE IN CMOS TECHNOLOGIES
AND ANALYSIS OF ADDER CIRCUITS USING LEAR SLEEP TECHNIQUE IN CMOS TECHNOLOGIES Aishwarya.S #1, Ravi.T *2, Kannan.V #3 # Department of ECE, Jeppiaar Institute of Technology, Chennai,Tamilnadu,India. 1 s.aishwaryavlsi@gmail.com
More informationDesign of an Efficient Low Power Multi Modulus Prescaler
International Journal of Engineering Research and Development e-issn: 2278-067X, p-issn: 2278-800X, www.ijerd.com Volume 6, Issue 3 (March 2013), PP. 15-22 Design of an Efficient Low Power Multi Modulus
More informationInternational Journal of Scientific & Engineering Research, Volume 5, Issue 11, November-2014 ISSN
790 Design Deep Submicron Technology Architecture of High Speed Pseudo n-mos Level Conversion Flip-Flop BIKKE SWAROOPA, SREENIVASULU MAMILLA. Abstract: Power has become primary constraint for both high
More informationLOW-POWER CLOCK DISTRIBUTION IN EDGE TRIGGERED FLIP-FLOP
LOW-POWER CLOCK DISTRIBUTION IN EDGE TRIGGERED FLIP-FLOP Rahul Yadav 1, Rahul Shrivastava 2, Vijay Yadav 3 1 M.Tech Scholar, 2 Asst. Prof., 3 Asst. Prof Department of Electronics and Communication Engineering,
More informationDesign Project: Designing a Viterbi Decoder (PART I)
Digital Integrated Circuits A Design Perspective 2/e Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolić Chapters 6 and 11 Design Project: Designing a Viterbi Decoder (PART I) 1. Designing a Viterbi
More information